共查询到18条相似文献,搜索用时 53 毫秒
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基于高速波形数字化实现高精度时间测量是核与粒子物理实验读出电子学中的研究热点。本工作针对高精度时间测量的需求基于实验室自主研发的开关电容阵列(Switched Capacitor Array, SCA)专用集成电路(Application Specific Integrated Circuit,ASIC)开展16通道集成的时间测量电子学原型的设计,输入信号经过SCA采样和量化后传输至现场可编程逻辑阵列(Field Programmable Gate Array, FPGA),在FPGA中进行误差修正、时间内插和数字甄别提取出时间信息。目前已在实验室环境下完成此电子学的时间精度测试,测试结果表明,此电子学可以实现好于10 ps RMS(Root Mean Square)的时间精度。 相似文献
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高速开关电容阵列(SCA)具有高速采样、低功耗的特点,基于SCA的高速波形数字化是目前高精度时间测量的一个重要研究方向。为此,我们开展SCA芯片的研究,目前已设计完成原型ASIC设计,并正在进行后续版本的改进设计。为便于未来多版本ASIC的测试和评估,需设计具有一定通用性的数字读出模块,本论文工作主要介绍此模块的设计工作以及相应的数据读出软件。数字读出模块基于FPGA实现对待测ASIC的控制、配置及数据读出,采用DDR3片外存储芯片,使用USB3.0等接口进行数据传输;上位机软件基于Python3.7设计,实现了数据采集与波形绘制等功能。目前已使用设计完成的数字读出模块对第2版SCA ASIC进行了初步的测试,测试结果表明,此读出模块工作正常,且SCA芯片输出结果符合预期。 相似文献
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随着高速波形数字化技术在核与粒子物理实验中的广泛应用,其对于ADC速度和精度需求日益增大,从而使电子学系统的PCB布局布线更加复杂、成本更高。为了简化设计,降低成本,提出了用于波形数字化的JESD204B的高速接口设计方法,介绍了JESD204B接口的协议及需求,并提出了基于Altera FPGA和专用JESD204B时钟芯片LMK0482x的具体解决方案。测试结果表明,时钟性能优异且JESD204B链路功能正常,系统性能优异,该方法可以实现JESD204B高速接口设计,并应用于波形数字化技术。At present, due to the wide application of nuclear and particle physics experiments in the waveform digitization technology and the increasing demand of high speed and high accuracy for ADC, the PCB layout is more and more complex and the cost is higher. In order to simplify the design and reduce the cost, this paper put forward the scheme of JESD204B high speed interface for the waveform digitization technology in nuclear and particle physics experiments. Firstly the interface protocol and the demand of JESD204B is introduced. Then the solution based on Altera FPGA and special JESD204B clock chip LMK0482x is proposed. The preliminary test results show that the clock performance is excellent and JESD204B link is functioning normally. Moreover, the system has an excellent performance. The scheme can realize the design of JESD204B high speed interface and therefore be applied to the waveform digitization technology. 相似文献
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Back-n是中国散裂中子源(CSNS)的反角中子束线,适用于精密核数据的测量。该装置的谱仪读出电子学采用共性化设计方法,利用高速波形数字化技术精密采集探测器输出信号波形。为完成对两通道、1 GSps,12 bit采样数据的读出和板载外设的控制,可以使用一种基于FPGA的高速数据实时读出方法。该方法不仅实现了数据接收、缓存上传等通用需求,还通过软件配置满足了实时触发处理等针对特定物理实验的特性需求。此外,FPGA的灵活使通过固件更新支持新实验或添加新功能成为可能。测试结果表明,该方法能够适应Back-n波形数字化模块高速数据读出的需求,峰值处理能力可达24 Gbps,符合物理实验需求。目前,基于实时读出方法实现的波形数字化模块已完成中子源谱仪实验现场的安装,工作稳定。Back-n is a back-streaming beam line at China Spallation Neutron Source, which is suitable for measure nuclear data precisely. The readout electronics of the spectrometers at this facility adopts general-propose design method, using high-speed waveform digitizing technology to record the detector output signal accurately. To read out two channels, 1 GSps, 12 bit sample data and control on-board devices, the real-time readout method of high-speed data based on FPGA technology can be considered. The method not only realizes the general requirements of the data upload, but also processes real-time triggers according to experiments via configuration. In addition, due to the flexibility of FPGAs, new experiments or new features can be supported through firmware updates. The test results show that the method is suitable for the high-speed data readout of field digitizing module at Back-n and peak capacity reaches up to 24 Gbps, which meets the requirements of the physical experiment. The field digitizing modules based on this method were installed at Back-n and work normally. 相似文献
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SCAs(Switched Capacitor Arrays) have a wide range of uses, especially in high energy physics, nuclear science and astrophysics experiments. This paper presents a method of using a MOS capacitor as a sampling capacitor to gain larger capacitance with small capacitor area in SCA design. It studies the non-ideal effects of the MOS capacitor and comes up with ways to reduce these adverse effects. A prototype SCA ASIC which uses a MOS capacitor to store the samples has been designed and tested to verify this method. The SCA integrates 32 channels and each has 64 cells and a readout amplifier. The stored voltage is converted to a pair of differential currents( 4m A max) and multiplexed to the output. All the functionalities have been verified. The power consumption is less than 2 m W/ch. The INL of all the cells in one channel are better than 0.39%. The equivalent input noise of the SCA has been tested to be 2.2 m V with 625 k Hz full-scale sine wave as input, sampling at 40 MSPS(Mega-samples per Second) and reading out at 5 MHz. The effective resolution is 8.8 bits considering 1 V dynamic range. The maximum sampling rate reaches up to 50 MSPS and readout rate of 15 MHz to keep noise smaller than 2.5 m V. The test results validate the feasibility of the MOS capacitor. 相似文献
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基于旋转二维发光二极管阵列的体三维显示系统 总被引:16,自引:0,他引:16
利用发光二极管 (LED)的高速发光特性 ,以旋转的二维发光二极管阵列为显示载体 ,通过时分寻址电路快速显示三维形体的二维截面序列。受调制的离散二维图像信息 ,因视觉暂留而形成深度效应 ,将被整合感知为一幅连续的三维图像。成功实现了具有 4 915 2个体像素 ,尺寸为14 4 .6mm× 110mm的柱体空间内的三维显示 ,图像具有双目视差、调节、会聚等常规视差信息 ,能提供真实的深度暗示 ,可同时从任意角度直接观察。论述了系统的显示原理及图像编码分解方法 ,分析和讨论了显示质量与体像素优化选取、起始位置显示信息的关联程度 相似文献
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在分析e2v公司的CCD47—20 Backthinned NIMO型CCD器件驱动时序关系的基础上,结合空间面阵CCD相机电子系统的总体要求,完成了基于FPGA的驱动时序发生器与下位机的一体化设计。选用FPGA器件作为硬件设计载体,使用VHDL语言对一体化的时序与控制通信系统进行了硬件描述。针对ALTERA公司的FPGA器件EP1C6Q240C8对设计进行了RTL级仿真及配置,完成了一体化系统的硬件电路。硬件实验结果表明,所研制的基于FPGA的一体化的时序与控制通信系统不仅可以满足CCD芯片和视频处理的时序要求,还可以与CCD相机上位机进行可靠的串行通信,监测和控制相机的工作状态. 相似文献
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红外光学系统决定着红外系统的工作模式与工作精度,影响系统的作用距离,是红外系统的重要组成部分。多视场光学系统可以用不同的视场对同一目标进行搜索、识别、跟踪与瞄准,在军事应用领域获得了广泛的应用。光学系统的结构形式影响红外系统的成像质量、性能指标、外形尺寸、价格成本、机电复杂程度等,因此研究和选取合适的多视场光学系统结构形式显得非常重要。对目前国内外应用于凝视焦平面探测器的多视场红外光学系统结构形式,如切换变焦、光学补偿变焦、机械补偿变焦、混合变焦、双光路变焦等进行了特点分析,比较了其优点与局限性,对光学设计人员合理选用多视场光学系统结构形式具有一定的理论指导作用和意义。 相似文献