An ultra low-power DAC with fixed output common mode voltage

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (V_cm) of the DAC remains fixed for all the digital codes. This feature helps a lot to improve the linearity of a typical SAR ADC and reduce the power consumption of comparator. The layout of the proposed DAC is very simple and easy to extend in contrast to the binary weighted CDACs where the layout needs lots of care and time. Several Monte-Carlo and Post-Layout simulations using CMOS 0.18 μm technology prove the benefits of the proposed CDAC. The proposed CDAC reduces the power consumption by 99.8% while enhances the speed and linearity of the comparator in a SAR ADC.     

Three-level inverter configuration with common mode voltage elimination for induction motor drive

A scheme for a three-level voltage space phasor generation with common-mode voltage elimination is proposed. An open-end-winding induction motor, fed from both ends by two three-level inverters, which are realized by a cascading two two-level inverter, is used in this configuration. The voltage space vectors of individual three- level inverters, which generate the same common mode voltage in the inverter pole voltage, are variously grouped When these voltage space vectors are used to switch individual three-level inverters, it results in zero commonmode voltage across the motor windings. In the proposed scheme, voltage space phasors from individual inverters with zero common mode voltage in the inverter pole voltage are used for PWM control. For the proposed drive configuration, the DC link voltage requirement is only half when compared to the DC link voltage of a conventional neutral-point-clamped （NPC） three-level inverter. The proposed inverter configuration offers reduced circuit and control complexity when compared to similar schemes with NPC or H-bridge inverter configurations.     

A common mode voltage reduction in boost rectifier/inverter systemby shifting active voltage vector in a control period

This paper proposes a new space-vector pulse width modulation (SVPWM) strategy that can reduce the number of common mode voltage pulses in a three-phase boost rectifier/inverter system using a synchronized switching sequence. In the proposed SVPWM strategy, it is possible to eliminate one common mode voltage pulse in every control period by shifting the active voltage vectors of the inverter to align to those of the boost rectifier. Thus, a reduction in the total number of common mode voltage pulses and RMS motor leakage current can be obtained without extra hardware. Since the proposed SVPWM strategy can be simply implemented in software, it is widely applicable regardless of the power capacity of the converter and results in no increment of converter volume, weight and price. Moreover, because the proposed SVPWM strategy maintains the magnitude of the active voltage vector required for motor control and simply changes the distribution of the zero, voltage vector, it does not effect the control performance of the power converter     

A dual two-level inverter scheme with common mode voltage elimination for an induction motor drive

Pulse-width modulated (PWM) inverters are known to generate common mode voltages which cause motor bearing currents in the induction motor drives. They also result in leakage currents which act as sources of conducted electromagnetic interference in the drive system. The common mode voltage generated by a conventional three-level inverter can be eliminated by switching only the voltage space vectors which do not produce the common mode voltage. This paper presents a PWM switching strategy to eliminate common mode voltage using the open-end winding configuration for the induction motor. The switching strategy presented in this paper, does not generate any alternating common mode voltages in the drive system and hence the electrostatic coupling of the common mode voltage, which results in the bearing currents and the leakage currents, is avoided. The proposed scheme is devoid of neutral point voltage fluctuations and does not require neutral point clamping diodes, when compared to the common mode elimination scheme based on the conventional three-level inverter topology. Also, the present scheme uses a single dc-link with half the voltage compared to the conventional three-level inverter based scheme.     

The uni-polarity phase-shifted controlled voltage mode AC-AC converters with high frequency AC link

A circuit configuration and circuit topological family of voltage mode ac-ac converters with high frequency ac links, which are based on forward converters, and a uni-polarity phase-shifted control strategy are proposed and deeply investigated. These kinds of converters consist of a input cycloconverter, a high frequency transformer, an output cycloconverter, input and output filters, and can transfer an unsteady ac voltage with a high harmonic into steady same-frequency ac sinusoidal voltage with a low harmonic. By using uni-polarity phase-shifted control strategy, output filtering inductance current is naturally commutated, and zero voltage switching of the output cycloconverter is realized. The converters' averaging model, the output characteristic curve, and design criteria for the key circuit parameters are given. The theoretical analysis and test result of 1kVA 220V /spl plusmn/ 10% 50Hzac/110V 50Hz ac prototype have shown that the converters have such advantages as high frequency electrical isolation, simple topology, two-stage power conversion (LFAC/HFAC/LFAC), bidirectional power flow, uni-polarity synchronized pulsewidth modulation waveform, high efficiency, high power density, high steady precision, low total harmonic distortion of the output voltage, strong adaptability to various loads, high line power factor, and low audio noise etc.     

A novel high voltage start up circuit for an integrated switched mode power supply

A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply(SMPS) is presented.An enhanced mode VDMOS transistor,the gate of which is biased by a floating pisland, is used to provide start up current and sustain high voltage.An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS.Simulation results indicate that the high voltage start up circuit can start and restart as designe...     

一种新型的用于开关电源的高压启动电路

文章提出了一种给集成开关电源提供初始电压的高压启动电路。一个增强型的VDMOS晶体管被用来提供启动电流和承受高压。VDMOS的栅被一个浮空P岛偏置。启动电路用了一个具有高的源对地击穿电压的NMOS来获得大的偏置电压范围。仿真结果表明高压启动电路能够按照设计正常的启动和重启动。本文提出的结构比起其它方案来更节能,成本更低。     

Electronically controlled high input and low output impedance voltage mode multifunction filter with grounded capacitors

In this study, a three-input single-output voltage-mode biquadratic filter employing voltage differencing differential input buffered amplifier (VD-DIBA) is presented. The proposed filter uses two VD-DIBAs and two grounded capacitors without any external resistors, which is well suited for integrated circuit implementation. The circuit provides five standard transfer functions, namely, low pass, high pass, band pass, notch and all pass filters with electronic control of quality factor and pole frequency. Each transfer function can be selected by suitably selecting input signals via digital method. The filter does not require inverting of the input voltage signal. Moreover, the circuit possesses high input and low output impedances and thus it enables simple voltage-mode cascading. The PSPICE simulation and also experimental results are included, verifying the workability of the proposed filter. The given results agree well with the theoretical anticipation.     

Analysis of common mode voltage-“neutral shift” inmedium voltage PWM adjustable speed drive (MV-ASD) systems

In this paper, an analysis of common mode voltage or “neutral lift” in the new emerging voltage source inverter type medium voltage adjustable speed drive (MV-ASD) systems is presented. Both cascaded multilevel (CML) inverter and 3-level NPC inverter topologies are analyzed. An equivalent circuit model to determine the common mode voltage stress is presented. Analysis and simulation results are discussed and worst case common mode voltage excursion is computed for an example 800 hp, 4160 V MV-ASD. It is shown that certain system components are excessively stressed and in the MV-ASD system these data are particularly useful in specifying system components and for proper design of the system. Possible effects of common mode voltage and its dv/dt on medium voltage motor bearings are discussed. A new multilevel PWM strategy is introduced which results in zero common-mode voltage. Simulation results are shown to illustrate the effectiveness of these schemes. Finally, experimental results from a 800 hp, 4160 V, MV-ASD system are presented     

Low voltage,high CMRR,and wide bandwidth novel current mode current controlled instrumentation amplifier

In this paper, a new current controlled instrumentation amplifier structure is proposed. The introduced circuit uses three current controlled conveyors and a single grounded resistor. This structure offers several enhanced advantages in comparison with other current and voltage modes instrumentation amplifiers. It provides attractive features such as: wide bandwidth independent to the differential gain, current tuned gain, high common mode rejection ratio without requiring matched resistors and low supply voltage equal to ±0.75 V. Accordingly, the proposed amplifier is a suitable element for integrated circuit implementation in the medical field. The used second-generation current controlled conveyor has a very simple structure. It is generally constituted of two NPN and seven CMOS transistors and it has numerous interesting characteristics. Theoretical analysis is carried out taking into consideration the non-ideality parameters of the conveyors. The circuit features are corroborated via a PSPICE simulation; the results are also compared to those of the previous structures presented in the literature.     

自动选择工作模式的宽范围稳压器

图1所示电路可在外部DAC（未示出）控制下为EEPROM提供编程电压。您可以用一个电位器来代替该DAC，以建立从12V电源上工作并能提供OV～32V可变输出电压的通用电源。如图1所示，凌特科技公司（Linear Technology）的LT1072HV型可变升压开关稳压器IC1，驱动一个由运放IC2、升压级Q3及发射极跟随器达灵顿晶体管Q2组成的A类放大器。电阻器R9和R10将放大器的正相环路增益设定为1＋（R9／R10）。     

单相电压型准阻抗源AC-AC变换器

为了克服传统AC-AC变换器的不足,提出一种新型的电压型准阻抗源AC-AC变换电路。研究了电路基本结构、工作原理,采用脉冲宽度调制(PWM)法对电路进行总体控制改变输出电压,给出了Matlab/Simulink下系统电路的仿真结果,最后在仿真的基础上利用TMS320F2812搭建了实验电路。实验结果验证了电路结构的可靠性和可行性。     

三相电压型准阻抗源AC～AC变换器

摘要：为了克服传统三相斩控式交流调压器的不足,提出了一种三相电压型准阻抗源变换器电路拓扑。研究了其拓扑结构和工作原理,推导了输出电压与占空比的定量关系。运用matlab对电路进行了仿真,并根据仿真结果建立了实验电路,采用脉冲宽度调制法（PWM）对电路进行总体控制,得到占空比为0.2与0.8时的三相电压波形。实验结果验证了三相电压型准阻抗源电压调节的的可靠性和可行性。     

A high voltage UMOS transistor

A throretical and experimental study of a novel UMOS (U for U-shaped notch) transistor structure is presented. This short channel device combines a simple U-groove geometry with features similar to those of DMOS transistors. Voltage and switching capabilities are investigated. Necessary trade-offs are emphasized in the design process and the critical fabrication steps are discussed.Both the theoretical considerations as well as the experimental results indicate that the UMOS transistor described is suitable for high voltage switching applications.     

A high voltage MOS switch

A novel MOS high voltage switch suitable for use in integrated circuits is described. The device doubles the operational voltage capability, compared to the standard MOS transistor used in integrated circuits. It uses a unique variable positive feedback which increases dramatically its saturation current and permits significant saving of the circuit area. The switch is fabricated using common Sigate technology. No additional processing steps are required.     

高压电子显微镜的发展

本文介绍了高压电子显微镜的发展历史、现状以及应用情况和对未来的展望。     

非接触式高压验电器的开发

文章介绍了非接触式验电器的工作原理和结构,并对现场中出现的问题进行了分析和解决,通过实际中的应用验证了设计原理的正确性     

一种电流镜型的BICOMS带隙基准电压源

传统的带隙基准源电路中存在运算放大器，其性能指标在很大程度上受到运放失调电压（Offset）、运放电源电压抑制比（PSRR）等参数的限制。要想进一步其性能，就需在电路结构上进行改进。 为此，笔者设计了一种新型基准源电路，其采用电流镜复制技术，没有使用运算放大器，避免了运放输入失调和电源抑制比的限制，并利用深度负反馈技术，极大地提高了电源抑制比。