BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

The SCC BJT: a high-performance bipolar transistor compatible withhigh-density deep-submicrometer BiCMOS SRAM technologies

We present the process development and device characterization of the Selectively Compensated Collector (SCC) BJT specifically designed for high-density deep-submicrometer BiCMOS SRAM technologies. This double-poly BJT takes advantage of the self-aligned polysilicon layers of the SRAM bit cell to obtain high performance without adding excessive process complexity. Furthermore, although an NPN device, the SCC BJT is formed in a lightly doped p-well in which the collector is formed with a single 370 keV phosphorus implant to minimize parasitic junction capacitances without the use of trench isolation or recessed oxides. The suitability of this bipolar structure outside of its original FSRAM intent is proven with its potential for bipolar logic and mixed-mode RF applications. ECL delays of 50 ps at 200 μA and a CML power-delay product of 4.5 fJ at 1.1 V supply were obtained. A 900 MHz noise figure as low as 0.54 dB at 0.5 mA with an associated gain of 14.7 dB was demonstrated as well as a dual modulus ÷4/5 prescaler operating up to 3.3 GHz for a switch current of 200 μA     

A 180 MHz 0.8 μm BiCMOS modular memory family of DRAM andmultiport SRAM

A family of modular memories with a built-in self-test interface designed using a synchronous self-timed architecture is described. This approach is ideally suited to modular memories embedded within synchronous systems due to its simple boundary specification, excellent speed/power performance, and ease of modelling. The basic port design is self-contained and extensible to any number of ports sharing access to a common-core cell array. The same design has been used to implement modular one-, two-, and four-part SRAMs and a one-port DRAM based on a four-transistor (4-T) cell. The latter provides a 45% core cell density improvement over the one-port SRAM. Nominal access and cycle times of 5.5 ns for 64 kb blocks have been shown for a 0.8 μm BiCMOS process with no memory process enhancements. System operation at 100 MHz has been demonstrated on a broadband time-switch chip containing 96 kb of two-port SRAM     

A high performance 0.35-μm 3.3-V BiCMOS technology optimized forproduct porting from a 0.6-μm 3.3-V BiCMOS technology

A 0.35-μm logic technology has been developed with high performance transistors and four layers of planarized metal interconnect. A 2.5-V version offers lower power and higher performance. A 3.3-V BiCMOS version has been optimized for compatibility with previous designs implemented in a 0.6-μm 3.3-V BiCMOS process. A two-step design process for converting an existing production worthy 0.6-μm 3.3-V BiCMOS design to a 0.35-μm design is described. The silicon results are described     

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOStechnologies

In this paper, the performance and reliability characteristics of the 0.35 μm/0.25 μm High Injection MOS (HIMIOS(R)) technology is described in detail. This flash EEPROM technology relies on source-side injection for programming and Fowler-Nordheim tunneling for erasing, and has been successfully implemented in a 1 Mbit memory array embedded in a 0.35 μm CMOS technology, adding only about 30% to the processing cost of digital CMOS. Due to its triple gate structure, the HIMOS(R) cell exhibits a high degree of flexibility and scalability. A fast programming operation (10 μs) at 3.3 V supply voltage is combined with an endurance of well over 100000 program/erase cycles, immunity to all possible disturb effects and a retention time that largely exceeds 100 years at 125°C. Furthermore, the cell has been scaled to a 0.25 μm version, which is a laterally scaled version with the same operating voltages and tunnel oxide thickness. The use of secondary impact ionization is investigated as well and proves to be very promising for future generations when the supply voltage is scaled below 2.5 V     

A low-capacitance bipolar/BiCMOS isolation technology. II. Circuitperformance and device self-heating

For pt. 1 see ibid., vol. 41, no. 8, p. 1379-87 (1994). Device and circuit results from transistors fabricated with a novel bipolar isolation technology are presented and discussed. The isolation structure, called sequentially planarized interlevel isolation technology (SPIRIT), is fabricated by using a combination of selective epitaxial growth of silicon and a preferential polishing technique as the key process elements. This structural concept aims for reduced collector-substrate and collector-base capacitances, as well as a lower extrinsic base contact resistance, in a partial-SOI structure without significantly increasing the device temperature during operation. The feasibility of the isolation structure is demonstrated through ECL ring oscillators with gate delays of 23.6 ps at 0.72 mA and 47 ps at 0.23 mA. The temperature contours for SPIRIT and other bipolar isolation structures are simulated by using a finite-element method. It is shown that the capacitance versus self-heating tradeoff of SPIRIT is significantly improved over that of conventional trench or SOI isolation structures     

A scaled 0.25-μm bipolar technology using full e-beamlithography

The full leverage offered by electron-beam lithography has been exploited in a scaled 0.25-μm double polysilicon bipolar technology. Devices and circuits were fabricated using e-beam lithography for all mask levels with level-to-level overlays tighter than 0.06 μm. Ion implantation was used to form a sub-100-nm intrinsic base profile, and a novel in-situ doped polysilicon emitter process was used to minimize narrow emitter effects. Transistors with 0.25-μm emitter width have current gains above 80 and cutoff frequencies as high as 40 GHz. A record ECL gate delay of 20.8 ps at 4.82 mW has been measured together with a minimum power-delay product of 47 fJ (42.1 ps at 1.12 mW). These results demonstrate the feasibility and resultant performance leverage of aggressive scaling of conventional bipolar technologies     

A high-performance 0.5-μm BiCMOS technology for fast 4-Mb SRAMs

A high-performance 0.5-μm BiCMOS technology has been developed. Three layers of polysilicon are used to achieve a compact four-transistor SRAM bit cell size of less than 20 μm² by creating self-aligned bit-sense and V_ss contacts. A WSi_x polycide emitter n-p-n transistor with an emitter area of 0.8×2.4 μm² provides a peak cutoff frequency (f_T) of 14 GHz with a collector-emitter breakdown voltage (BV_CFO) of 6.5 V. A selectively ion-implanted collector (SIC) is used to compensate the base channeling tail in order to increase f_T and knee current without significantly affecting collector-substrate capacitance. ECL gate delays as fast as 105 ps can be obtained with this process     

A low-cost horizontal current bipolar transistor (HCBT) technology for the BiCMOS integration with FinFETs

A novel Horizontal Current Bipolar Transistor (HCBT) is processed with the scaled down dimensions and the improved technology. The active transistor region is built in the defect-free sidewall of the 580 nm wide n-hills in the (1 1 0) wafer, implying the reduction of the parasitic region's volume, i.e. the extrinsic base and the collector. The fabricated HCBT exhibits the cutoff frequency (f_T) of 21.4 GHz, the maximum frequency of oscillations (f_max) of 32.6 GHz and the collector–emitter breakdown voltage (BV_CEO) of 5.6 V, which are the highest f_T and the highest f_TBV_CEO product among the lateral bipolar transistors (LBTs).     

Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

The implementation of high voltage vertical bipolar transistors in a BiCMOS technology requires sufficient space for the extension of the collector-base depletion region. Assuming that layout design rules for high voltage devices are used, the open base breakdown voltage BV_ceo is only defined by the one-dimensional vertical doping profile through the n⁺-emitter, the p-base, the n-intrinsic and the n⁺-extrinsic collector, i.e. lateral effects can be neglected for this type of brakdown. This paper describes the derivation of simple equations for optimizing the n⁺pn⁻n⁺-structure. Closed-form analytical equations based on the impact ionization model from Fulop ([1] Solid St. Electron. 10, 39 (1967)) yield the dependence of the open base breakdown voltage BV_ceo on the transistor gain, doping level and width of the intrinsic collector.     

U-grooved SIT CMOS technology with 3 fJ and 49 ps (7 mW, 350 fJ)operation

Static induction transistor (SIT) CMOS is analyzed by a circuit simulation method. According to the results, the propagation delay time of the SIT CMOS could be represented as the ratio of the load capacitance to the transconductance. The U-grooved structure plays an important role in the fabrication of MOS SIT with large transconductance and small parasitic capacitance. U-grooved SIT CMOS has been fabricated by anisotropic plasma etching, and its switching speed has been evaluated by a 31-stage ring oscillator. A minimum ρ-τ product of 3 fJ/gate has been obtained for a design rule of 1-μm channel length. A minimum propagation delay time of 49 ps/gate has also been obtained at a dissipation power of 7 mW/gate, which corresponds to a ρ-τ product of 350 fJ/gate     

A low-capacitance bipolar/BiCMOS isolation technology. I. Concept,fabrication process, and characterization

A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to ≃30%, the collector-base capacitance to ≃70%, and the extrinsic base contact resistance to <50% compared to trench isolation. The combination of SEG and polishing makes it possible to form SOI regions with locally different SOI thicknesses on the same wafer, so that fully depleted CMOS and vertical bipolar transistors can be combined in a SOI-BiCMOS technology     

A 32-word by 32-bit three-port bipolar register file implementedusing a SiGe HBT BiCMOS technology

Describes a novel system level design for a 32-word by 32-bit bipolar register file with two read ports and one write port. The register file is implemented using a SiGe HBT BiCMOS technology and emitter-coupled logic (ECL)-style circuits. It has dimensions of 1.0 mm by 1.8 mm. The read access time for the register Me is between 340 and 350 ps using read port A, while the read access time using read port B is between 360 and 380 ps. Read access times as low as 290 ps were measured for some columns, however. The write access time for the register file is between 250 and 340 ps, using a write enable pulse with a width between 130 and 170 ps. The estimated register file power dissipation is 4.7 W using a 4.5-V supply     

Device characteristics of 0.35 μm P-channel DINOR flash memoryusing band-to-band tunneling-induced hot electron (BBHE)programming

The P-channel DINOR flash memory, which uses the band-to-band tunneling induced hot electron (BBHE) program method having the advantages of high scalability, high efficiency, and high oxide reliability, was fabricated by 0.35-μm-rule CMOS process and was investigated in detail. An ultra-high programming throughput of less than 8 ns/byte (=4 μs/512 byte) and a low current consumption of less than 250 μA were achieved by utilizing 512-byte parallel programming. Furthermore, we investigated its endurance characteristics up to 10⁶ program/erase cycles, and window narrowing and G_m degradation were found to be very small even after 10⁶ cycles. It is thought that the BBHE injection point contributes to the G _m stability and the oxide-damage-reduced operation contributes to the good window narrowing characteristics. The P-channel DINOR flash memory realizing high programming throughput with low power consumption is one of the strongest candidates for the next generation of high-performance, low-voltage flash memories     

Fully integrated concurrent dual-band low noise amplifier with suspended inductors in SiGe 0.35 μm BiCMOS technology

A fully integrated concurrent dual-band low noise amplifier with suspended inductors is reported. Wideband input impedance matching and wideband low noise characteristics are achieved by the proposed capacitive feedback technique simultaneously. Measurement results show input return losses of -12.8 and -11.5 dB, voltage gains of 14.4 and 14.3 dB, and noise figures of 2.5 and 3.0 measured at 2.3 and 4.5 GHz, respectively, with an image rejection ratio of 26.1 dB and power consumption of 11.9 mW.     

A low-voltage CMOS complementary active pixel sensor (CAPS)fabricated using a 0.25 μm CMOS technology

A low voltage rail-to-rail CMOS complementary active pixel sensor (CAPS) architecture is presented. Compared with a conventional active pixel sensor (APS), the CAPS surpasses the bottleneck of limited output swing at ultra-low supply voltage operation imposed by highly scaled technology, making it more scalable compared with other reported architectures. The CAPS has been implemented with a commercially available 0.25 μm CMOS technology. The pixel size of the fabricated CAPS is 12 μm × 10 μm with a fill factor of 30%. It is verified that the CAPS is capable to operate at a V_DD below 1 V with a reasonable output swing     

A micromachined electrical field-flow fractionation (μ-EFFF)system

Micromachining technologies are employed to develop a miniaturized electrical field-flow fractionation (EFFF) separation system. EFFF systems are used to separate colloidal particles such as cells, liposomes, proteins, or other particulates, and to characterize emulsions and other mixtures according to particle charge density. Macromachining techniques have been used to develop existing EFFF technologies. At the present time, the limiting factor in the development of higher precision EFFF separation systems has been the manufacturing approach. In this paper, the theory behind the operation and resolution of a micron-sized EFFF (μ-EFFF) system is described and the advantages to be gained from application of micromachining technologies are given, thus motivating the need for further miniaturization. A completely fabricated μ-EFFF system is developed, separations are performed, and the μ-EFFF system is compared to the theoretically predicted results as well as the results from current macro EFFF systems     

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II—Latchup

CMOS latchup and electrostatic discharge (ESD) continue to be a semiconductor quality and reliability area of interest as semiconductor components continue to be reduced to smaller dimensions. The combination of scaling, design integration, circuit performance objectives, new applications, and the evolving system environments, CMOS latchup and ESD robustness will continue to be a technology concern. With both the revolutionary and evolutionary changes in CMOS and Silicon Germanium semiconductor technologies, and changing product environments, new CMOS latchup and ESD requirements also continue in semiconductor design, device and chip-level simulation, design verification, chip-to-system evaluation, and the need for new latchup and ESD test specifications. Additionally, the issues of low cost, low power and radio frequency (RF) GHz performance objectives has lead to both revolutionary as well as derivative technologies; these have opened new doors for discovery, development and research in the area of latchup and ESD. Although latchup and ESD are not a new reliability arena, there are also new issues rising each year, making the latchup and ESD an area of continuous discovery, innovation and invention. In this paper, an introduction to latchup in CMOS and BiCMOS Silicon Germanium will be discussed.     

A compact low noise operational amplifier for a 1.2 μm digitalCMOS technology

A compact low noise operational amplifier using lateral p-n-p bipolar transistors in the input stage has been fabricated in a standard 1.2 μm digital n-well CMOS process. Like their n-p-n counterparts in p-well processes, these lateral p-n-p transistors exhibit low 1/f noise and good lateral β. The fabricated op amp has an area of only 0.211 mm² with E_n=3.2 nV/√(Hz), I_n=0.73 pA/√(Hz), E_n and I_n 1/f noise corner frequencies less than 100 Hz, a -3 dB bandwidth greater than 10 MHz with a closed loop gain of 20.8 dB, a minimum PSRR (DC) of 68 dB, a CMRR (DC) of 100 dB, a minimum output slew rate of 39 V/μs, and a quiescent current of 2.1 mA at supply voltages of ±2.5 V. The operational amplifier drives a 1 kΩ resistive load to 1 V peak-to-peak at 10 MHz and has been used as a versatile building block for mixed-signal IC designs     

AWG-based device for a WDM overlay PON in the 1.5 μm band

A novel concept has been developed for overlaying a power-splitting passive optical network (PON) in one wavelength band with a wavelength-division-multiplexed (WDM) PON in another wavelength band. An eight-channel device fabricated in silica technique shows an insertion loss of 3.5 dB and a crosstalk of -23 dB for the WDM channels around 1.55 μm wavelength. The 1 to 8 splitting function at 1.50 μm wavelength has an additional penalty of -1 dB and a uniformity of ±0.5 dB