共查询到20条相似文献,搜索用时 15 毫秒
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D. J. Meyer D. A. Webb M. G. Ward J. D. Sellar P. Y. Zeng J. Robinson 《Materials Science in Semiconductor Processing》2001,4(6)
The continued growth of high-speed-digital data transmission and wireless communications technology has motivated increased integration levels for ICs serving these markets. Further, the increasing use of portable wireless communications tools requiring long battery lifetimes necessitates low power consumption by the semiconductor devices within these tools. The SiGe and SiGe:C materials systems provide solutions to both of these market needs in that they are fully monolithically integratible with Si BiCMOS technology. Also, the use of SiGe or SiGe:C HBTs for the high-frequency bipolar elements in the BiCMOS circuits results in greatly decreased power consumption when compared to Si BJT devices.Either a DFT (graded Ge content across the base) or a true HBT (constant Ge content across the base) bipolar transistor can be fabricated using SiGe or SiGe:C. Historically, the graded profile has been favored in the industry since the average Ge content in the pseudomorphic base is less than that of a true HBT and, therefore, the DFT is tolerant of higher thermal budget processing after deposition of the base. The inclusion of small amounts of C (e.g. <0.5%) in SiGe is effective in suppressing the diffusion of B such that very narrow extremely heavily doped base regions can be built. Thus the fT and fmax of a SiGe:C HBT/DFT are capable of being much higher than that of a SiGe HBT/DFT.The growth of the base region can be accomplished by either nonselective mixed deposition or by selective epitaxy. The nonselective process has the advantage of reduced complexity, higher deposition rate and, therefore, higher productivity than the selective epitaxy process. The selective epi process, however, requires fewer changes to an existing fabrication sequence in order to accommodate SiGe or SiGe:C HBT/DFT devices into the BiCMOS circuit. 相似文献
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L.K. Nanver V. Jovanovi C. Biasotto J. Moers D. Grützmacher J.J. Zhang N. Hrauda M. Stoffel F. Pezzoli O.G. Schmidt L. Miglio H. Kosina A. Marzegalli G. Vastola G. Mussler J. Stangl G. Bauer J. van der Cingel E. Bonera 《Solid-state electronics》2011,60(1):75-83
The potentials of using silicon-germanium dots as stressor material in MOSFETs are evaluated with respect to integration in today’s production processes. Work is reviewed that has lead to the fabrication of the first experimental n-channel MOSFETs on SiGe dots, referred to as DotFETs, in a low-complexity, custom-made low-temperature process where the dot is preserved during the entire device processing. The SiGe dots were grown in large regular arrays in a Stranski-Krastanow (S-K) mode and used to induce biaxial tensile strain in a silicon capping-layer. The DotFETs are processed with the main gate-segment above the strained Si layer on a single dot. To prevent intermixing of the Si/SiGe/Si structure, the processing temperature is kept below 400 °C by using excimer-laser annealing to activate the source/drain implants that are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing and, compared to reference devices, an average increase in drain current up to 22.5% is obtained. The experimental results are substantiated by extensive simulations and modeling of the strain levels in capped dots and the corresponding mobility enhancement achievable with DotFETs. The concept of SiGe dots overgrown with a Si layer is also considered for use as a starting structure for silicon-on-nothing (SON) technology where the dot should be removed after the formation of the gate-stack and the strain for mobility enhancement should be preserved (and possibly increased) via the other device layers. 相似文献
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A simple technique leading to the measurement of minority carrier lifetimes of UHV compatible LPCVD Si and SiGe by C–t depth profiling of Metal:Oxide:Si:SiGe:Si structures is reported. A high quality gate oxide is realised by low temperature (<100°C) plasma anodisation thereby reducing any oxidation effects on the underlying epitaxial layer quality. Capacitance response times were observed for an impurity concentration of 2.5×1017 cm−3, giving rise to generation lifetimes of the Si and Si0.9Ge0.1 of >0.55 and 2.6 μs respectively, reflective of very high quality epitaxial semiconductor material. 相似文献
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针对铂等常用金属热敏材料电阻温度系数(TCR)不高,导致热式MEMS流速传感器宽量程测量时功耗高的问题,设计了 一种基于非晶锗(a-Ge)薄膜热电阻的低功耗、宽量程柔性MEMS流速传感器.非晶锗热电阻材料具有较高的TCR系数(约为-0.02/K)和室温电阻率(5Ω·m),传感器在较低的工作温差和功耗下可获得宽量程的流速测量.阐述了该柔性MEMS流速传感器的设计结构、工作原理、3D有限元建模和热-流场仿真结果.利用聚酰亚胺衬底空腔膜上的四个非晶锗热电阻同时作为自加热热源和测温元件.四个非晶锗热电阻组成一个惠斯通电桥,同时结合热损失和热温差原理来实现宽量程流速测量和测向.仿真结果表明,惠斯通电桥采用恒电流供电只需120μA,使得非晶锗热阻的工作温度与环境温度之间的温差不高于6 K,就可对0~50 m/s范围内的流速进行测量,且功耗在1.368 mW以内.该柔性流速传感器易于采用MEMS技术批量制造,可贴于曲面应用,非常适于物联网等低功耗流速传感领域. 相似文献
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The high aspect-ratio combined poly- and single-crystal silicon micromachining technology (HARPSS) and its application to fabrication of precision MEMS inertial sensors are presented. HARPSS is a single wafer, all silicon, front-side release process which is capable of producing 10–100's of microns thick, electrically isolated, 3-D poly- and single-crystalline silicon microstructures with various size air-gaps ranging from sub-micron to tens of microns. High aspect-ratio (>50:1) polysilicon structures are created by refilling 100's of microns deep trenches with polysilicon deposited over a sacrificial oxide layer. This technology provides features required for precision micromachined inertial sensors. The all-silicon feature of this technology improves long term stability and temperature sensitivity while fabrication of large area, vertical electrodes with sub-micron gap spacing will increase the sensitivity by orders of magnitude. 相似文献
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MEMS独特的结构和特性,给划片工艺带来了巨大的挑战.介绍了传统砂轮划片技术在MEMS芯片生产中的局限性,指出了隐形激光划片技术的优越性,综述了激光划片技术在MEMS划片中的应用,对几种较成熟的先进激光划片技术进行了比较,对各自的工作原理、特点、工序作了重点阐述,并对MEMS划片技术的发展前景作了展望. 相似文献
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Silicon nano-wires were fabricated using thin Silicon on Insulator (SOI) wafers and a combination of anisotropic wet etching by Tetra-Methyl Ammonium Hydroxide (TMAH) and Local Oxidation of Silicon (LOCOS). These nano-wires were submitted to laser exposure using gas immersion laser doping (GILD). The result was the formation of either periodic nano-structures or silicon balls. Since the process uses very short laser pulses, it involves rapid melting and solidification of silicon. Hence, the observed periodicity is ascribed to Rayleigh instability, which involves surface tension effects in melted silicon. 相似文献
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介绍了一种利用激光多普勒(LD)技术和显微技术结合的微机电系统(MEMS)器件动态特性测量技术,所搭建的系统测量光斑直径小于1um,测量频率0~20MHz,平面外运动分辨率0.1nm,精度5nm,不确定度1nm描述了利用该系统对TMT(test motion target)器件的振动特性进行的测量实验,并对实验结果进行了分析,测得器件的共振频率为271Hz,最大振幅为0.246482566mm。 相似文献
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电子系统设计高度集成和小体积化趋势要求时钟产品向小体积,薄型化方向发展,但在此过程中,传统石英或压电陶瓷材料的时钟产品受制于物理特性,其可靠性、精度和高性能之间的平衡很难保持,传统材料的易碎性,在厚度小于0.8mm时其抗冲击、震动能力都大受影响,使得传统材料的薄型化产品面临着高成本及低良率的问题。 相似文献
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Embedded benzocyclobutene in silicon: An integrated fabrication process for electrical and thermal isolation in MEMS 总被引:1,自引:0,他引:1
Alireza Modafe 《Microelectronic Engineering》2005,82(2):154-167
This paper reports a novel fabrication process to develop planarized isolated islands of benzocyclobutene (BCB) polymer embedded in a silicon substrate. Embedded BCB in silicon (EBiS) can be used as an alternative to silicon dioxide in fabrication of electrostatic micromotors, microgenerators, and other microelectromechanical devices. EBiS takes advantage of the low dielectric constant and thermal conductivity of BCB polymers to develop electrical and thermal isolation integrated in silicon. The process involves conventional microfabrication techniques such as photolithography, deep reactive ion etching, and chemical mechanical planarization (CMP). We have characterized CMP of BCB polymers in detail since CMP is a key step in EBiS process. Atomic force microscopy (AFM) and elipsometry of blanket BCB films before and after CMP show that higher polishing down force pressure and speed lead to higher removal rate at the expense of higher surface roughness, non-uniformity, and scratch density. This is expected since BCB is a softer material compared to inorganic films such as silicon dioxide. We have observed that as the cure temperature of BCB increases beyond 200 °C, the CMP removal rate decreases drastically. The results from optical microscopy, scanning electron microscopy, and optical profilometry show excellent planarized surfaces on the EBiS islands. An average step height reduction of more than 95% was achieved after two BCB deposition and three CMP steps. 相似文献
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This paper reports on the design, fabrication and testing of novel one and two port piezoelectric higher order contour-mode MEMS resonators that can be employed in RF wireless communications as frequency reference elements or arranged in arrays to form banks of multi-frequency filters. The paper offers a comparison of one and two port resonant devices exhibiting frequencies approximately ranging from 200 to 800 MHz, quality factor of few thousands (1000–2500) and motional resistances ranging from 25 to 1000 Ω. Fundamental advantages and limitations of each solution are discussed. The reported experimental results focus on the response of a higher order one port resonator under different environmental conditions and a new class of two port contour resonators for narrow band filtering applications. Furthermore, an overview of novel frequency synthesis schemes that can be enabled by these contour-mode resonators is briefly presented. 相似文献