Oscillation-based test in oversampled ΣΔ modulators

This paper discusses a way of applying the oscillation-based test (OBT)/oscillation-based built-in-self test concept to oversampled ΣΔ modulators, exploiting previous experience coined through the implementation of OBT in SC integrated filters. Analytical and simulation results demonstrate that it is always feasible to find out an OBT configuration for a typical discrete-time second-order modulator structure without adding a substantial extra circuitry, but only resorting to local feedback loops. A feedback strategy can be chosen providing enough freedom to force oscillations, which can be worthwhile for testing purposes. The selected oscillation parameters allow us to establish criteria for a high fault coverage.     

Test of switched-capacitor ladder filters using OBT

In this paper, a way to test switched-capacitors ladder filters by means of Oscillation-Based Test (OBT) methodology is proposed. Third-order low-pass Butterworth and Elliptic filters are considered in order to prove the feasibility of the proposed approach. A topology with a non-linear element in an additional feedback loop is employed for converting the Circuit Under Test (CUT) into an oscillator. The idea is inspired in some author's previous works (G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Oscillation-based Test Experiments in Filters: a DTMF example, in: Proceedings of the International Mixed-Signal Testing Workshop (IMSTW'99), British Columbia, Canada, 1999, pp. 249–254; G. Huertas, D. Vazquez, E. Peralías, A. Rueda, J.L. Huertas, Oscillation-based test in oversampling A/D converters, Microelectronic Journal 33(10) (2002) 799–806; G. Huertas, D. Vázquez, E. Peralías, A. Rueda. J.L. Huertas, Oscillation-based test in bandpass oversampled A/D converters, in: Proceedings of the International Mixed-Signal Test Workshop, June 2002, Montreaux (Switzerland), pp. 39–48; G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Practical oscillation-based test of integrated filters, IEEE Design and Test of Computers 19(6) (2002) 64–72; G. Huertas, D. Vázquez, E. Peralías, A. Rueda, J.L. Huertas, Testing mixed-signal cores: practical oscillation-based test in an analog macrocell, IEEE Design and Test of Computers 19(6) (2002) 73–82). Two methods are used, the describing function approach for the treatment of the non linearity and the root-locus method for analysing the circuit and predicting the oscillation frequency and the oscillation amplitude. In order to establish the accuracy of these predictions, the oscillators have been implemented in SWITCAP (K. Suyama, S.C. Fang, Users' Manual for SWITCAP2 Version 1.1, Columbia University, New York, 1992). Results of a catastrophic fault injection in switches and capacitors of the filter structure are reported. A specification-driven fault list for capacitors is also defined based on the sensitivity analysis. The ability of OBT for detecting this kind of faults is presented.     

Oscillation-based test in digital shapers

We address the problem of testing digital shapers used for nuclear spectroscopy. Particularly, we propose a solution based on the oscillation-based test (OBT) for testing the finite impulse response (FIR) filters of the shaper. The OBT strategy developed here exploits the natural partition of the system in high-pass and low-pass sections for implementing two different non-linear oscillators. The oscillation parameters are obtained in advance using two different approaches: one based on the filter signal flow-graph; the other based on the describing function technique. The fault simulation results show high fault coverage and acceptable test time. Additionally, we suggest the use of this test strategy in a BIST environment, because it does not need resources for pattern generation and presents both low system intrusion and low hardware overhead.     

On configurable oversampled A/D converters

An oversampled A/D (analog-to-digital) converter that can be configured as either a sigma-delta converter or an incremental converter is presented. This is an oversampled instrumentation converter that cancels offset and 1/f noise. The converter architecture is based on a mixed analog-digital integrator (MADI) concept. This concept is shown to lead to a very simple and modular architecture. The implemented converter also allows selection of the converter order and the decimation factor in order to find the best tradeoff between resolution, conversion time or bandwidth, and power consumption. As the converter architecture is completely modular, it can rapidly be tailored for a specific application with minimized silicon area. The circuit achieves a resolution of 16 b on a range of ±650 mV and compensates the offset and the even-order harmonics to a nonobservable level     

Digital implementation of mismatch shaping in oversampled pipelineA/D converters

Pipeline A/D converters are usually implemented with switched capacitor technology. The effect of gain errors caused by capacitor mismatch may be attenuated using mismatch-shaping techniques. The author introduces an architecture that improves the SFDR of a particular pipeline A/D converter, simply by adding digital hardware to the existing analogue design     

Multibit oversampled ΣΔ A/D converters as front end forCD players

A technique is presented for deriving all of the different control signals needed for focusing and radial tracking in a digital servosystem for compact disc (CD) players, as well as the full band data from the disc. Because of the different natures of all those signals, different bandwidth and dynamic range, complex analog anti-aliasing circuits, and several types of A/D (analog-to-digital) converters would normally be required to convert the signals from the analog to digital domain. With the proposed technique it is possible to carry out the conversion of the high-frequency data as well as the low-frequency control signals with only a single type of multibit sigma-delta (ΣΔ) A/D converter in combination with digital signal processing. The use of ΣΔ type A/D conversion also has other advantages such as its suitability for integration in a CMOS VLSI process and the fact that the requirements for the anti-aliasing filters in front of the converters are relaxed due to the oversampling technique     

Reducing test application time, test data volume and test power through Virtual Chain Partition

A new scan approach is described, named ‘Virtual Chain Partition’ (VCP) architecture, capable of substantially reducing the test application time, test data volume and test power. The VCP architecture maintains the original scan cell order. A simple procedure is proposed, which uses the scan test set generated for the original circuit to determine the maximum reduction in test cycles obtainable with the architecture and to select the most suitable configuration for each circuit. The experiments carried out with the ISCAS 89 benchmarks show that the VCP architecture allows considerable reductions to be achieved both for single and multiple scan chain circuits.     

On simple oversampled A/D conversion in shift-invariant spaces

It has been found that the quantization error e for a conventional oversampled analog-to-digital (A/D) conversion behaves like /spl par/e/spl par//sup 2/=O(/spl tau//sup 2/) with respect to the sampling rate /spl tau/. Recently, conventional A/D conversion has been extended to A/D conversion based on shift-invariant spaces. As consequences of such extension, it offers rich choices to build a nonideal A/D conversion system of high accuracy and low computational complexity, as well as reduces the noise sensitivity and computational complexity in digital-to-analog (D/A) conversion. Therefore, it is necessary to establish the estimate of quantization error for the extended A/D conversion based on shift-invariant spaces. In this paper, we introduce a constructive method to establish an estimate of the quantization error as |e|/sup 2/=O(/spl tau//sup 2/) for oversampled A/D conversion in shift-invariant spaces. Meanwhile, we demonstrate that the bit rate required to encode the converted digital signal in such A/D conversion scheme only increases as the logarithm of the sampling ratio. Therefore, the quantization error is an exponentially decaying function of the bit rate. In order to establish such an estimate, we need the nonuniform sampling theorem for shift-invariant spaces, which, as the necessary preparation, is studied prior to introducing the constructive method.     

Short test procedures for R-2R D/A converters by electrical modeling and application of the ambiguity algorithm

A reduced physical model of the integral non-linearity error in high resolution R-2R D/A converters is obtained by circuit analysis and application of the ambiguity algorithm. Its relationships with the well establisheda priori model based on Rademacher functions is discussed. Experiments, carried out on a sample of commercial 12 bit converters, demonstrate that functional test programs based on this model achieve shorter test times and lower prediction errors than those based on larger models obtained by straight QR factorization.     

Signal folding in A/D converters

Signal folding appears in A/D converters (ADCs) in various ways. In this paper, the evolution of this technique is derived from the fundamentals of quantization to obtain systematic insights. We look upon folding as an automatic multiplexing of zero crossings, which simplifies hardware while preserving the high speed and low latency of a flash ADC. By appreciating similarities between the well-known pipeline ADCs, folding ADCs, and ripple through ADCs, this enables the circuit designer to more freely choose the best architecture to meet the specified performance goals.     

Finite state machine synthesis with fault tolerant test function

According to a recent synthesis for testability proposal, a test function specified as a finite state machine with the same number of state variables as the given object machine, is incorporated into the state diagram prior to synthesis. Since a complete verification of the test machine is not practical, an often used heuristic sets and observes each state variable. The two machines share logic and a fault can result in partial or total loss of the test function. We show that the tests generated under the assumption that the entire test function is intact can become invalid. We propose a new method of synthesizing PLA-based finite state machines with fault tolerant test machines. Our approach eliminates testing of the test function. A constrained logic minimization phase insures that faults have predictable effect on the state diagram of the composite machine (object machine embedded with the test function). This allows effective use of the test function during test generation even in the presence of faults that effect both object and test machines. Only a combinational test generator is required for test generation. Each combinational vector is augmented by appropriate initialization and propagation sequences. Unlike prior approaches, ourO(log₂ n) length test sequence isguaranteed to detect any targeted crosspoint fault. Experimental results on the MCNC Logic Synthesis Workshop finite state machine benchmark set are given as evidence of practicality of the proposed approach.Supported by C&C Research Laboratories, NEC USA, during summer 1991.     

集成电路测试相关标准研究与探讨

重点研究了纯数字信号、混合信号和片上系统测试的一些问题及相关标准，阐述了各标准的作用，分析了这些标准在实际应用中存在的一些问题及其局限性。     

Trimless high precision ratioed resistors in D/A and A/D converters

Investigations into realization of high precision ratioed resistors in standard CMOS and BiCMOS processes have been carried out. The results indicate that the layout of the resistors can be optimized with respect to area and matching requirements to yield relative accuracy better than 0.25%. Using an intermeshed ladder architecture, fast converters with resolution up to 10 b are realizable without trimming     

Finite state machine synthesis with embedded test function

We propose a synthesis for a testability method in which the test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as an FSM with the same number of state variables as the given object machine. Based upon the chosen test methodology, a variety of test functions can be defined. As an illustration, we construct a test machine in which each state is uniquely set and observed by an input sequence no longer than log _k n, wheren is the number of states and the integerk is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization, and technology mapping are carried out for the combined graph. By design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements, the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.     

Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.     

AD转换器全码测试的研究与实现

本文主要探讨AD转换器全码测试的原理及实现方法,并说明了如何基于国产JC-3165测试系统完成对AD转换器的静态参数的测试。AD转换器全码测试模块包含高精度电压源、高精度波形产生器、ADC输出码存储器3大部分。高精度电压源提供AD转换器的电压基准;高精度波形产生器提供AD转换器的模拟交流或直流输入电压;存储器用于存储AD转换器的数字输出数据;最后让测试系统中的图形控制器和定时产生器与全码测试模块同步工作,同时存储输出码;分析输出码即可得出DNL、INL等参数。     

基于SOC的PAGER控制芯片设计

文章讨论了PAGER控制器芯片（ZQD021）的系统设计，该控制器内部集成了FLASH，SRAM，POCSAG协议解码器和嵌入式MCU CORE。重点分析了芯片的可测性设计（DFT），内嵌FLASH设计，低功耗设计，其设计方法和思路对消费类和嵌入式控制芯片的设计有一定的借鉴意义。     

CMOS charge-transfer preamplifier for offset-fluctuationcancellation in low-power A/D converters

We have developed a low-power, high-accuracy comparator composed of a dynamic latch and a CMOS charge transfer preamplifier (CT preamplifier). The CT preamplifier amplifies the input signal with no static power dissipation, and the operation is almost insensitive to the device parameter fluctuations. The low-power and high-accuracy comparator has been realized by combining the CT preamplifier with a dynamic latch circuit. The fluctuation in the offset voltage of a dynamic latch is reduced by a factor of the preamplifier gain. A 4-bit flash A/D converter circuit has been designed and fabricated by 0.6-μm CMOS process. Low differential nonlinearity of less than ±4 mV has been verified by the measurements on test circuits, showing 8-bit resolution capability. Very low power operation at 4.3 μW per MS/s per comparator has also been achieved     

Static linearity error analysis of subranging A/D converters

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate f _sand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.     

介绍一种检查和消除微机A／D D／A通道数据误差的方法

本文介绍了一种采用硬/软件结合消除微机A/D、D/A通道数据误差的方法,所加硬件均为普通元器件,造价低,且软件开销也不大,这对提高微机系统的性能价格比,推广应用微机新产品均有益处。