Unified built-in self-test for fully differential analog circuits

The reduction of test costs, especially in high safety systems, requires that the same test strategy is employed for design validation, manufacturing and maintenance tests, and concurrent error detection. This unification of off-line and on-line tests has already been attempted for digital circuits and it offers the advantage of serving to all phases of a system lifetime.Market pressure originating from the high costs of analog and mixed signal testing has resulted in renewed efforts for the test of analog parts. In this paper, off-line and on-line test techniques for fully differential analog circuits are presented within an unified approach. The high performance of these circuits makes them very popular for many applications, including high safety, low voltage and high speed systems.A test master compliant with IEEE Std. 1149.1 is described. The Analog Unified BIST (AUBIST) is exemplified for linear and non-linear switched-capacitor circuits. High fault coverage is achieved during concurrent/on-line testing. An off-line test ensures the goal of self-checking circuits and allows the diagnosis of faulty parts. The self-test of the AUBIST circuitry is also considered.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

On-chip measurement of waveforms in mixed-signal circuits using a segmented subsampling technique

This paper presents a circuit technique for the design of a wideband on-chip sampling oscilloscope in mixed-signal integrated circuits. A coupled Phase Locked Loop (PLL) and Delay Locked Loop (DLL) module is designed to generate a high-resolution sampling clock over a limited time interval. This module has been employed as an enabling circuit to support on-chip measurement of fast waveforms through a subsampling technique attaining less than 10 ps sampling resolution. Input waveforms are first divided into equal-size-segments in the time domain and then each segment is subsampled with the sampling clock supplied by the coupled PLL and DLL module. The proposed measurement scheme has been fabricated in CMOS 0.18 μm technology and the measurement results indicate that over 7 effective bits of measurement linearity can be achieved for input signals up to 1.6 GHz.     

Noise-Insensitive Digital BIST for any PLL or DLL

PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, phase error, output frequency, duty cycle, lock time, and lock range. Two techniques for cancelling random and systematic noise are also described. The multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.

Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets

An automatic test pattern generation (ATPG) procedure for linear analog circuits is presented in this work. A fault-based multifrequency test approach is considered. The procedure selects a minimal set of test measures and generates the minimal set of frequency tests which guarantee maximum fault coverage and, if required, maximal fault diagnosis, of circuit AC hard/soft faults. The procedure is most suitable for linear time-invariant circuits which present significant frequency-dependent fault effects.For test generation, the approach is applicable once parametric tests have determined DC behaviour. The advantage of this procedure with respect to previous works is that it guarantees a minimal size test set. For fault diagnosis, a fault dictionary containing a signature of the effects of each fault in the frequency domain is used. Fault location and fault identification can be achieved without the need of analog test points, and just in-circuit checkers with an observable go/no-go digital output are required for diagnosis.The procedure is exemplified for the case of an analog biquadratic filter. Three different self-test approaches for this circuit are considered. For each self-test strategy, a set of several test measures is possible. The procedure selects, in each case, the minimal set of test measures and the minimal set of frequency tests which guarantee maximum fault coverage and maximal diagnosis. With this, the self-test approaches are compared in terms of the fault coverage and the fault diagnosability achieved.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

一种数模混合电路状态的波形分析方法

本文针对数模混合电路仿真波形的特点,提出一种以开关事件为基础的状态序列数据结构,有效地压缩存储空间;同时,基于这种数据结构,本文还提出一种仿真波形比较方法,该方法根据仿真波形自动检测划分电路的状态,并能在考虑一定容限范围的前提下实现波形比较,有效地提高了模拟信号以及数字信号完整性的验证效率.这种方法已成功运用到本文开发的数模混合时移波形比较软件系统中,并已在Intel技术开发(上海)公司内部推广使用.     

Investigation of the optimum oscillation frequency value towards increasing the efficiency of OBIST approach

This paper is mainly focused on the investigation of the optimum value of the oscillation frequency in the Oscillation-based Built-In Self Tests (OBIST). It has been assumed that the proper frequency value might increase the test efficiency in covering hard-detectable short faults in analog integrated circuits (ICs) designed in nanoscale technology. In our research, active analog filters designed in 0.35 μm and 90 nm CMOS technologies were used as circuits under test (CUT). The tested circuits were brought to oscillation at different oscillation frequencies by varying the values of passive devices. The achieved results prove that the efficiency of OBIST approach can be increased in this way.     

Low Cost On-Line Testing Strategy for RF Circuits

This work proposes the use of a simple 1-bit digitizer as an analog block observer, in order to enable the implementation of on-line test strategies for RF analog circuits in the System-on-Chip environment. The main advantages of using a simple digitizer for RF circuits are related to the increased observability of the RF signal path and minimum RF signal degradation, as neither reconfiguration of the signal path nor variable load for the analog RF circuit are introduced. As an additional advantage, the same digitizer can be used to implement BIST strategies, if required. The feasibility of using a 1-bit digitizer for the test of analog signals has already been presented in the literature for low frequency linear analog systems. This paper discusses the implementation of an on-line test strategy for analog RF circuits in the SoC environment, and presents new results for on-line RF testing. Moreover, we also provide detailed analysis regarding the overhead of the test strategy implementation. Experimental results illustrate the feasibility of the proposed technique.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A. Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in VLSI Architecture and is also thesis director. His main research interests are integrated circuit architecture, embedded systems, signal processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.     

Test of switched-capacitor ladder filters using OBT

In this paper, a way to test switched-capacitors ladder filters by means of Oscillation-Based Test (OBT) methodology is proposed. Third-order low-pass Butterworth and Elliptic filters are considered in order to prove the feasibility of the proposed approach. A topology with a non-linear element in an additional feedback loop is employed for converting the Circuit Under Test (CUT) into an oscillator. The idea is inspired in some author's previous works (G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Oscillation-based Test Experiments in Filters: a DTMF example, in: Proceedings of the International Mixed-Signal Testing Workshop (IMSTW'99), British Columbia, Canada, 1999, pp. 249–254; G. Huertas, D. Vazquez, E. Peralías, A. Rueda, J.L. Huertas, Oscillation-based test in oversampling A/D converters, Microelectronic Journal 33(10) (2002) 799–806; G. Huertas, D. Vázquez, E. Peralías, A. Rueda. J.L. Huertas, Oscillation-based test in bandpass oversampled A/D converters, in: Proceedings of the International Mixed-Signal Test Workshop, June 2002, Montreaux (Switzerland), pp. 39–48; G. Huertas, D. Vázquez, A. Rueda, J.L. Huertas, Practical oscillation-based test of integrated filters, IEEE Design and Test of Computers 19(6) (2002) 64–72; G. Huertas, D. Vázquez, E. Peralías, A. Rueda, J.L. Huertas, Testing mixed-signal cores: practical oscillation-based test in an analog macrocell, IEEE Design and Test of Computers 19(6) (2002) 73–82). Two methods are used, the describing function approach for the treatment of the non linearity and the root-locus method for analysing the circuit and predicting the oscillation frequency and the oscillation amplitude. In order to establish the accuracy of these predictions, the oscillators have been implemented in SWITCAP (K. Suyama, S.C. Fang, Users' Manual for SWITCAP2 Version 1.1, Columbia University, New York, 1992). Results of a catastrophic fault injection in switches and capacitors of the filter structure are reported. A specification-driven fault list for capacitors is also defined based on the sensitivity analysis. The ability of OBT for detecting this kind of faults is presented.     

Trimming analog circuits using floating-gate analog MOS memory

A floating-gate MOS analog memory circuit that can be electrically programmed for positive and negative voltage changes and that can be fabricated in a standard CMOS IC process is described. Unlike existing electrically erasable floating-gate memory circuits, this circuit does not require special fabrication techniques like ultrathin tunneling oxides or textured polysilicon. Instead, mask geometry is used to cause field-enhanced Fowler-Nordheim tunneling of electrons from a floating gate. Retention measurements at elevated temperatures indicate that the loss of floating-gate charge should be less than 0.1% over a ten-year period at temperatures below 100°C. One limitation of this structure is that the rate of change of the floating-gate voltage can be quite small (e.g. 10 mV/s). A general trimming circuits, whose novel feature is that any number of trimming circuits can be independently and simultaneously adjusted across an entire IC, has been incorporated into a prototype CMOS op amp to decrease its input offset voltage from 10 mV to less than 0.5 mV     

一种有效的ADC内建自测试方案

内建自测试是降低ADC电路测试成本的有效方法。通过最小二乘法和斜坡柱状图。我们得出了测试ADC电路的增益误差、失调误差、微分非线性和积分非线性的算法。根据这些测试算法。介绍了一种易于片上集成的内建自测试结构。实验结果表明，该内建自测试方案具有较高的测试精度。     

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.     

Test generation for specification test of analog circuits using efficient test response observation methods

In this paper, a new automated test generation methodology for specification testing of analog circuits using test point selection and efficient analog test response waveform capture methods for enhancing the test accuracy is proposed. The proposed approach co-optimizes the construction of a multi-tone sinusoidal test stimulus and the selection of the best set of test response observation points. For embedded analog circuits, it uses a subsampling-based digitization method compatible with IEEE 1149.1 to accurately digitize the analog test response waveforms. The proposed specification approach uses ‘alternate test’ framework, in which the specifications of the analog circuit-under-test are computed (predicted) using statistical regression models that are constructed based on process variations and corresponding variations of test responses captured from different test observation points. The test generation process and the test point selection process aim to maximize the accuracy of specification prediction. Experimental results validating the proposed specification test approach are presented.     

用于SOC测试的一种有效的BIST方法

为了提高SOC芯片的可测性和可靠性,我们提出了一种SOC测试的BIST技术的实现方案.针对某所自行研制的数字模拟混合信号SOC芯片,我们使用了不同的可测性技术.比如对模拟模块使用改进的BIST方法,对嵌入式存储器使用了MBIST技术.一系列的测试实验数据表明,该BIST方法能有效提高测试覆盖率.     

Optimization-based multifrequency test generation for analog circuits

A robust test set for analog circuits has to detect faults under maximal masking effects due to variations of circuit parameters in their tolerance box. In this paper we propose an optimization based multifrequency test generation method for detecting parametric faults in linear analog circuits. Given a set of performances and a frequency range, our approach selects the test frequencies that maximize the observability on a circuit performance of a parameter deviation under the worst masking effects of normal variations of the other parameters. Experimental results are provided and validated by HSpice simulations to illustrate the proposed approach.     

Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.     

Low Cost BIST for Static and Dynamic Testing of ADCs

This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5× in test time, in comparison to the histogram method.Maria da Gloria Cataldi Flores was born in Santa Maria, Brazil, in 1978. She received the electrical engineering degree in 2000 from Universidade Federal de Santa Maria (UFSM) and the M.S. degree engineering in 2003 from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then, she has been working as a design engineer in an EAS Supply brazilian company. Her main research interests include mixed-signal and analog testing and digital signal processing.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree engineering in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the M.Sc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr. Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible by courses in VLSI Architecture and is also thesis director. His main research interests are Integrated Circuit Architecture, Embedded Systems, Signal Processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.Felipe Ricardo Clayton received the B.S. degree in Electrical Engineering from State University of Campinas (UNICAMP), Brazil, in 1986. He worked at CPqD (Brazilian PTT R&D Center) till 1996 designing analog and mixed signal circuits for telecom and automotive applications. From 1997 to the second half of 1998, he worked at Instituto Superior Técnico (IST), Lisbon, Portugal, under the guidance of Prof. Carlos Azeredo Leme on development of CMOS RF circuits. Since October 1998 he had worked for Motorola SPS. Now he is head of the Power Managment Group at Freescale.Cristiano Benevento received his B.S. degree in Electrical Engineering from Universidade Estadual de Campinas (Unicamp), Brazil, in 1997. He worked at Motorola Cellular Infrastructure Group until August 2000 as a Systems Engineer. He joined Motorola Semiconductor Product Sector in August 2000 as IC Designer for Power Management Group and is now at Freescale.     

Defect detection in analog and mixed circuits by neural networks using wavelet analysis

An efficient defect-oriented parametric test method for analog & mixed-signal integrated circuits based on neural network classification of a selected circuit's parameter using wavelet decomposition preprocessing is proposed in this paper. The neural network has been used for detecting catastrophic defects in two experimental analog & mixed-signal CMOS circuits by sensing the abnormalities in selected parameters, observed under defective conditions and by their consequent classification into a proper category. To reduce complexity of the neural network, wavelet decomposition is used to perform preprocessing of the analyzed parameter. Moreover, we show that wavelet analysis brings significant enhancement in the correct classification, and makes the neural network-based test method extremely efficient & versatile for detecting hard-detectable catastrophic defects in analog & mixed-signal circuits.     

数模混合信号的测试与仿真

VLSI的发展特别是SoC的出现，对混合信号测试的研究提出了紧迫的要求。结合系统级芯片的可测试性设计技术所面临的技术难点．本文着重讨论了目前现有的各种测试手段及其各自的特点。