Fabrication and characterization of 4H—SiC bipolar junction transistor with double base epilayer

In this paper we report on a novel structure of a 4H-SiC bipolar junction transistor with a double base epilayer that is continuously grown.The measured dc common-emitter current gain is 16.8 at IC = 28.6 mA(J C = 183.4 A/cm2),and it increases with the collector current density increasing.The specific on-state resistance(Rsp-on) is32.3mΩ·cm 2 and the open-base breakdown voltage reaches 410 V.The emitter N-type specific contact resistance and N + emitter layer sheet resistance are 1.7×10-3 Ω·cm2 and 150 /,respectively.     

Investigation of current transport parameters of Ti/4H-SiC MPS diode with inhomogeneous barrier

The current transport parameters of 4H-SiC merged PiN Schottky(MPS) diode are investigated in a temperature range of 300-520 K.Evaluation of the experimental current-voltage(I-V) data reveals the decrease in Schottky barrier height Φ b but an increase in ideality factor n,with temperature decreasing,which suggests the presence of an inhomogeneous Schottky barrier.The current transport behaviours are analysed in detail using the Tung’s model and the effective area of the low barrier patches is extracted.It is found that small low barrier patches,making only 4.3% of the total contact,may significantly influence the device electrical characteristics due to the fact that a barrier height of 0.968 eV is much lower than the average barrier height 1.39 eV.This shows that ion implantation in the Schottky contact region of MPS structure may result in a poor Ti/4H-SiC interface quality.In addition,the temperature dependence of the specific on-resistance(R on sp),T 2.14,is determined between 300 K and 520 K,which is similar to that predicted by a reduction in electron mobility.     

Control of electric field in 4H-SiC UMOSFET: Physical investigation

In this paper, we show how breakdown voltage (V_BR) and the specific on-resistance (R_on) can be improved simply by controlling of the electric field in a power 4H-SiC UMOSFET. The key idea in this work is increasing the uniformity of the electric field profile by inserting a region with a graded doping density (GD region) in the drift region. The doping density of inserted region is decreased gradually from top to bottom, called Graded Doping Region UMOSFET (GDR-UMOSFET). The GD region results in a more uniform electric field profile in comparison with a conventional UMOSFET (C-UMOSFET) and a UMOSFET with an accumulation layer (AL-UMOSFET). This in turn improves breakdown voltage. Using two-dimensional two-carrier simulation, we demonstrate that the GDR-UMOSFET shows higher breakdown voltage and lower specific on-resistance. Our results show the maximum breakdown voltage of 1340 V is obtained for the GDR-UMOSFET with 10 µm drift region length, while at the same drift region length and approximated doping density, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 V and 703 V, respectively.     

Edge termination study and fabrication of a 4Hben SiC junction barrier Schottky diode

The 4H-SiC junction barrier Schottky (JBS) diodes terminated by field guard rings and offset field plate are designed, fabricated and characterized. It is shown experimentally that a 3-μm P-type implantation window spacing gives an optimum trade-off between forward drop voltage and leakage current density for these diodes, yielding a specific on-resistance of 8.3 mΩ·cm². A JBS diode with a turn-on voltage of 0.65 V and a reverse current density less than 1 A/cm² under 500 V is fabricated, and the reverse recovery time is tested to be 80 ns, and the peak reverse current is 28.1 mA. Temperature-dependent characteristics are also studied in a temperature range of 75 ℃-200 ℃. The diode shows a stable Schottky barrier height of up to 200 ℃ and a stable operation under a continuous forward current of 100 A/cm².     

具有部分超结的新型SiC SBD特性分析

提出了一种具有部分超结（super junction, SJ）结构的新型SiC肖特基二极管,命名为SiC Semi-SJ-SBD结构,通过将常规SBD耐压区分为常规耐压区和超结耐压区来减小导通电阻,改善正向特性.利用二维器件模拟软件MEDICI仿真分析,研究了不同超结深度和厚度时击穿电压(V_B)和比导通电阻(R_on-sp),与常规结构的SBD比较得出,半超结结构可以明显改善SiC肖特基二极管特性,并得到优化的设计方案,选择超结宽度2< 关键词： SiC肖特基二极管 super junction 导通电阻 击穿电压     

Study of a double epi-layers SiC junction barrier Schottky rectifiers embedded P layer in the drift region

<正>This paper proposes a double epi-layers 4H—SiC junction barrier Schottky rectifier(JBSR) with embedded P layer (EPL) in the drift region.The structure is characterized by the P-type layer formed in the n-type drift layer by epitaxial overgrowth process.The electric field and potential distribution are changed due to the buried P-layer,resulting in a high breakdown voltage(BV) and low specific on-resistance(R_(on,sp)).The influences of device parameters,such as the depth of the embedded P+ regions,the space between them and the doping concentration of the drift region,etc.,on BV and R_(on,sp) are investigated by simulations,which provides a particularly useful guideline for the optimal design of the device.The results indicate that BV is increased by 48.5%and Baliga's figure of merit(BFOM) is increased by 67.9%compared to a conventional 4H-SiC JBSR.     

A 4H-SiC trench MOSFET structure with wrap N-type pillar for low oxide field and enhanced switching performance

An optimized silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET) structure with side-wall p-type pillar (p-pillar) and wrap n-type pillar (n-pillar) in the n-drain was investigated by utilizing Silvaco TCAD simulations. The optimized structure mainly includes a p$+$ buried region, a light n-type current spreading layer (CSL), a p-type pillar region, and a wrapping n-type pillar region at the right and bottom of the p-pillar. The improved structure is named as SNPPT-MOS. The side-wall p-pillar region could better relieve the high electric field around the p$+$ shielding region and the gate oxide in the off-state mode. The wrapping n-pillar region and CSL can also effectively reduce the specific on-resistance ($R_{rm on,sp}$). As a result, the SNPPT-MOS structure exhibits that the figure of merit (FoM) related to the breakdown voltage ($V_{rm BR}$) and $R_{rm on,sp}$ ($V_{rm BR}^{2}R_{rm on,sp}$) of the SNPPT-MOS is improved by 44.5%, in comparison to that of the conventional trench gate SJ MOSFET (full-SJ-MOS). In addition, the SNPPT-MOS structure achieves a much faster-witching speed than the full-SJ-MOS, and the result indicates an appreciable reduction in the switching energy loss.     

Improvement of reverse blocking performance in vertical power MOSFETs with Schottky–drain-connected semisuperjunctions

To enhance the reverse blocking capability with low specific on-resistance,a novel vertical metal-oxidesemiconductor field-effect transistor(MOSFET) with a Schottky-drian(SD) and SD-connected semisuperjunctions(SDD-semi-SJ),named as SD-D-semi-SJ MOSFET is proposed and demonstrated by two-dimensional(2D) numerical simulations.The SD contacted with the n-pillar exhibits the Schottky-contact property,and that with the p-pillar the Ohmic-contact property.Based on these features,the SD-D-semi-SJ MOSFET could obviously overcome the great obstacle of the ineffectivity of the conventional superjunctions(SJ) or semisuperjunctions(semi-SJ) for the reverse applications and achieve a satisfactory trade-off between the reverse breakdown voltage(BV) and the specific on-resistance(R_(on)A).For a given pillar width and n-drift thickness,there exists a proper range of n-drift concentration(N),in which the SD-D-semi-SJ MOSFET could exhibit a better trade-off of R_(on)A-BV compared to the predication of SJ MOSFET in the forward applications.And what is much valuable,in this proper range of N,the desired BV and good trade-off could be achieved only by determining the pillar thickness,with the top assist layer thickness unchanged.Detailed analyses have been carried out to get physical insights into the intrinsic mechanism of R_(on)A-BV improvement in SD-D-semi-SJ MOSFET.These results demonstrate a great potential of SD-D-semi-SJ MOSFET in reverse applications.     

SiC晶体缺陷的阴极荧光无损表征研究

由于在研究SiC晶体缺陷对器件性能的影响的过程中,表征材料缺陷的常用的方法是破坏性的,因此寻找一种无损的测试方法对缺陷进行有效的表征显得尤为重要。基于阴极荧光(CL)的工作原理对4H-SiC同质外延材料的晶体缺陷进行了无损测试研究。结果发现利用阴极荧光可以观测到晶体内部的堆垛层错、刃位错和螺位错以及基面位错,其阴极荧光图中的形貌分别为直角三角形、点状和短棒状。因此该方法成为SiC晶体缺陷的无损表征时的一种有效的测试方法。如果利用该方法对材料的衬底和外延层缺陷分别进行观测就能建立起衬底和外延层缺陷之间的某种联系,另外对器件工作前后的缺陷进行表征,建立器件工作前后缺陷之间的联系,就可以进一步地研究材料缺陷对器件性能影响的问题。     

4H-SiC n-MOSFET的高温特性分析

通过考虑迁移率和阈值电压随温度的变化关系，模拟分析了4H-SiC n-MOSFET高温下的电学 特性，模拟结果与实验有较好的符合.并进一步讨论了主要结构参数和工艺参数对高温电特 性的影响及其最佳取值. 关键词： n-MOSFET 4H-SiC 迁移率 阈值电压     

Temperature-dependent characteristics of 4Hben SiC junction barrier Schottky diodes

The current-voltage characteristics of 4H-SiC junction barrier Schottky (JBS) diodes terminated by an offset field plate have been measured in the temperature range of 25-300 ℃. An experimental barrier height value of about 0.5 eV is obtained for the Ti/4H-SiC JBS diodes at room temperature. A decrease in the experimental barrier height and an increase in the ideality factor with decreasing temperature are shown. Reverse recovery testing also shows the temperature dependence of the peak recovery current density and the reverse recovery time. Finally, a discussion of reducing the reverse recovery time is presented.     

Characterization of 4Hben SiC substrates and epilayers by Fourier transform infrared reflectance spectroscopy

The infrared reflectance spectra of both 4H-SiC substrates and epilayers are measured in a wave number range from 400 cm^-1 to 4000 cm^-1 using a Fourier-transform spectrometer. The thicknesses of the 4H-SiC epilayers and the electrical properties, including the free-carrier concentrations and the mobilities of both the 4H-SiC substrates and the epilayers, are characterized through full line-shape fitting analyses. The correlations of the theoretical spectral profiles with the 4H-SiC electrical properties in the 30 cm^-1-4000 cm^-1 and 400 cm^-1-4000 cm^-1 spectral regions are established by introducing a parameter defined as error quadratic sum. It is indicated that their correlations become stronger at a higher carrier concentration and in a wider spectral region (30 cm^-1-4000 cm^-1). These results suggest that the infrared reflectance technique can be used to accurately determine the thicknesses of the epilayers and the carrier concentrations, and the mobilities of both lightly and heavily doped 4H-SiC wafers.     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.     

双外延基区4H-SiC BJTs的建模与仿真

基于4H-SiC的材料特性,对具有双外延基区结构的4H-SiC双极晶体管进行研究.通过分析该结构在基区内部形成的自建电场以及基区渡越时间,利用正交试验的方法,基于各种器件二维模型,对该器件结构进行数值计算,并进行平均极差分析.计算结果表明,该器件的共发射结电流增益最高可达72,具有负温度系数,并且在一个很宽的集电极电流范围内该特性保持不变.     

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance(Ron,sp) integrable silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer(BOX)(DGRD MOSFET).First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage(BV).The BV of 233 V and Ron,sp of 4.151 mΩ·cm2(VGS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.     

4H-SiC材料在紫外波段吸收系数的分析研究

基于已报道的4H-SiC材料在紫外波段(325—390nm)吸收系数的测定,结合经验公式,采用外推和多项式拟合方法分析4H-SiC材料在200—400nm紫外波段的吸收系数,并得到4H-SiC材料的吸收系数与波长的关系式。对4H-SiC吸收系数的分析研究将作为4H-SiC光电探测器结构设计的一个重要依据。     

结终端采用JTE保护技术的4H-SiC PiN二极管模拟和研制

利用二维器件模拟软件ISE-TCAD 10.0,对结终端采用结扩展保护技术的4H-SiC PiN二极管平面器件进行反向耐压特性的模拟,并获得许多有价值的模拟数据.依据所得的模拟数据进行此种二极管器件的研制.实验测试表明,此二极管的模拟优化数据与实验测试的结果一致性较好,4H-SiC PiN二极管所测得到的反向电压达1600 V,该反向耐压数值达到理想平面结的击穿耐压90%以上.     

Fabrication and characterization of the normally-off N-channel lateral 4H–SiC metal–oxide–semiconductor field-effect transistors

In this paper, the normally-off N-channel lateral 4H–Si C metal–oxide–semiconductor field-effect transistors(MOSFFETs) have been fabricated and characterized. A sandwich-(nitridation–oxidation–nitridation) type process was used to grow the gate dielectric film to obtain high channel mobility. The interface properties of 4H–Si C/SiO_2 were examined by the measurement of HF I–V, G–V, and C–V over a range of frequencies. The ideal C–V curve with little hysteresis and the frequency dispersion were observed. As a result, the interface state density near the conduction band edge of 4H–Si C was reduced to 2 × 10~(11) e V~(-1)·cm~(-2), the breakdown field of the grown oxides was about 9.8 MV/cm, the median peak fieldeffect mobility is about 32.5 cm~2·V~(-1)·s~(-1), and the maximum peak field-effect mobility of 38 cm~2·V~(-1)·s~(-1) was achieved in fabricated lateral 4H–Si C MOSFFETs.     

Synthesis and characterization of porous crystalline SiC thin films prepared by radio frequency reactive magnetron sputtering technique

Hexagonal SiC thin films have been deposited using radio frequency reactive magnetron sputtering technique by varying the substrate temperature and other deposition conditions. Prior to deposition surface modification of the substrate Si(1 0 0) played an important role in deposition of the hexagonal SiC structure. The effect of substrate temperature during deposition on structure, composition and surface morphology of the SiC films has been analyzed using atomic force microscopy, Fourier transform infrared spectroscopy and spectroscopic ellipsometry. X-ray diffraction in conventional θ-2θ mode and omega scan mode revealed that the deposited films were crystalline having 8H-SiC structure and crystallinity improved with increase of deposition temperature. The bonding order and Si-C composition within the films showed improvement with the increase of deposition temperature. The surface of thin films grew in the shape of globes and columns depending upon deposition temperature. The optical properties also showed improvement with increase of deposition temperature and the results obtained by ellipsometry reinforced the results of other techniques.