具有纵向漏极场板的低导通电阻绝缘体上硅横向双扩散金属氧化物半导体器件新结构

为降低绝缘体上硅(SOI)横向双扩散金属氧化物半导体(LDMOS)器件的导通电阻,同时提高器件击穿电压,提出了一种具有纵向漏极场板的低导通电阻槽栅槽漏SOI-LDMOS器件新结构.该结构特征为采用了槽栅槽漏结构,在纵向上扩展了电流传导区域,在横向上缩短了电流传导路径,降低了器件导通电阻;漏端采用了纵向漏极场板,该场板对漏端下方的电场进行了调制,从而减弱了漏极末端的高电场,提高了器件的击穿电压.利用二维数值仿真软件MEDICI对新结构与具有相同器件尺寸的传统SOI结构、槽栅SOI结构、槽栅槽漏SOI结构进行了比较.结果表明:在保证各自最高优值的条件下,与这三种结构相比,新结构的比导通电阻分别降低了53%,23%和提高了87%,击穿电压则分别提高了4%、降低了9%、提高了45%.比较四种结构的优值,具有纵向漏极场板的槽栅槽漏SOI结构优值最高,这表明在四种结构中新结构保持了较低导通电阻,同时又具有较高的击穿电压.     

Mismatch of dielectric constants at the interface of nanometer metal-oxide-semiconductor devices with high-<Emphasis Type="Italic">K</Emphasis> gate dielectric impacts on the inversion charge density

The comparison of the inversion electron density between a nanometer metal-oxide-semiconductor (MOS) device with high-K gate dielectric and a SiO₂ MOS device with the same equivalent oxide thickness has been discussed. A fully self-consistent solution of the coupled Schr?dinger–Poisson equations demonstrates that a larger dielectric-constant mismatch between the gate dielectric and silicon substrate can reduce electron density in the channel of a MOS device under inversion bias. Such a reduction in inversion electron density of the channel will increase with increase in gate voltage. A reduction in the charge density implies a reduction in the inversion electron density in the channel of a MOS device. It also implies that a larger dielectric constant of the gate dielectric might result in a reduction in the source–drain current and the gate leakage current.     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer(TSL) with linear variable doping(LVD) and further research on the TSL LVD with a multiple step field plate(MSFP),a breakdown voltage(BV) model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator(SOI) device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field(ENDIF),from which the reduced surface field(RESURF) condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection(HVI) line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET(nLDMOS) with MSFP is realized.The experimental breakdown voltage(BV) and specific on-resistance(R on,sp) of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.     

Photoelectric spectroscopy of oxide states with MOS structures atT=79 K

AtT=79 K illumination effects with visible and UV light on the drain current were studied forn-channel enhancement-type MOS transistors. The results show that the response of photoelectric measurements is due to electron excitation from oxide states into the silicon surface layer (positive changes of drain current). The oxide states lying near the bottom of the silicon dioxide conduction band are distributed in energy. Oxide states having captured a hole can be discharged by electrons excited from the silicon conduction or valence band (negative changes of drain current) in combination with a tunneling process.     

Variation of co-tunneling and Kondo effects by control of the strength of coupling between a vertical dot and a two-dimensional electron gas

We have fabricated a vertical quantum dot with lateral coupling, modulated by a split gate voltage, to a two-dimensional electron. We thereby control not only electron configurations but also the strength of coupling between the dot and the lateral lead, by applying gate voltages. We have measured the conductance enhancement when the applied bias exceeds the single-electron excitation energy, in the Coulomb blockade regime. This conductance enhancement disappears as the split gate voltage decreases (reducing the coupling). This indicates that this enhancement is caused by inelastic co-tunneling. Furthermore, we observed a conductance enhancement at zero source–drain bias with stronger coupling. An anomaly is observed that we attribute to Kondo resonance between the dot and the leads.     

Ultrathin gate dielectrics for silicon nanodevices

This paper reviews recent progress in structural and electronic characterizations of ultrathin SiO₂thermally grown on Si(100) surfaces and applications of such nanometer-thick gate oxides to advanced MOSFETs and quantum-dot MOS memory devices. Based on an accurate energy band profile determined for the n ⁺ -poly- Si/SiO₂/Si(100) system, the measured tunnel current through ultrathin gate oxides has been quantitatively explained by theory. From the detailed analysis of MOSFET characteristics, the scaling limit of gate oxide thickness is found to be 0.8 nm. Novel MOSFETs with a silicon quantum-dot floating gate embedded in the gate oxide have indicated the multiple-step electron injection to the dot, being interpreted in terms of Coulombic interaction among charged dots.     

Microscopic mechanism responsible for radiation-enhanced diffusion of impurity atoms

Modelling of radiation-enhanced diffusion (RED) of boron and phosphorus atoms during irradiation of silicon substrates respectively with high- and low-energy protons was carried out. The results obtained confirm the previously arrived conclusion that impurity diffusion occurs by means of the ‘impurity atom – intrinsic point defect’ pairs and that the condition of the local thermodynamic equilibrium between substitutional impurity atoms, nonequilibrium point defects created by irradiation, and the pairs is valid. It is shown that using RED, one can form a special impurity distribution in the semiconductor substrate including retrograde profiles with increasing impurity concentration in the bulk of the semiconductor. In addition, modelling of radiation-induced segregation of nitrogen implanted in stainless steel modified by titanium is carried out. It is shown that vacancy-impurity complexes are responsible for nitrogen diffusion in an implanted layer excluding the ‘tail’ region. The calculations performed give clear evidence in favour of further investigation of various doping processes based on RED, especially the processes of plasma doping, to develop a cheap method for forming specific impurity distributions in the near surface region.     

Modeling the Behavior of a MOS Transistor under Fast Neutron and Gamma Irradiation

A numerical model of trapping of the radiation-induced charge in the bulk and on the surface of the oxide layer of a MOS transistor has been developed. The model takes into account the generation of point defects under fast neutron irradiation. The volume and surface charges obtained by the numerical modeling have been used to calculate the drain—gate characteristic of the MOS transistor exposed to neutron irradiation in different doses and accompanying high-energy gamma-ray irradiation. To model the effect of neutron irradiation, different methods for estimating the rate of point defect generation in a two-component material (SiO2) have been developed. The simulated drain—gate characteristic is shown to agree well with the experimental data obtained at the concentration of hole traps and their capture cross sections lying within the published data for an unirradiated device after exposure to gamma rays from a 60Co gamma source and after irradiation with fast neutrons with an average energy of ∼1 MeV and accompanying gamma rays using a pool-type reactor.     

Influence of Ring Oxidation-Induced Stack Faults on Efficiency in Silicon Solar Cells

We observe a strong correlation between the ring oxidation-induced stack faults (OISF) formed in the course of phosphor diffusion and the efficiency of Czochralski-grown silicon solar cells. The main reason for ring-OISF formation and growth in substrate is the silicon oxidation and phosphorus diffusion process induced silicon self-interstitial point defect during POCl₃ diffusion. The decreasing of minority carrier diffusion length in crystal silicon solar cell induced by ring-OISF defects is identified to be one of the major causes of efficiency loss.     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.     

Numerical method for a 2D drift diffusion model arising in strained n-type MOSFET device

This paper reports the calculation of electron transport in metal oxide semiconductor field effects transistors (MOSFETs) with biaxially tensile strained silicon channel. The calculation is formulated based on two-dimensional drift diffusion model (DDM) including strain effects. The carrier mobility dependence on the lateral and vertical electric field model is especially considered in the formulation. By using the model presented here, numerical method based on finite difference approach is performed. The obtained results show that the presence of biaxially tensile strain enhances the current in the devices.     

Two-dimensional electrical characterization of ultrashallow source/drain extensions for nanoscale MOSFETs

State-of-the-art semiconductor devices require accurate control of the full two-dimensional dopant distribution. In this work, we report results obtained on 2D electrical characterization of ultra shallow junctions in Si using off axis electron holography to study two-dimensional effects on diffusion. In particular, the effect of a nitride diffusion mask on lateral diffusion of phosphorous is discussed. Retardation of lateral diffusion of P under the nitride diffusion mask is observed and compared to the lateral diffusion of P under an oxide diffusion mask. The ultra shallow junctions for the study were fabricated by a rapid thermal diffusion process from heavily P doped spin-on-dopants into a heavily B doped Si substrate. These shallow junctions are needed for fabricating source/drain extensions in nanoscale MOSFETs. One-dimensional electrical characterization of the junction was carried out to determine the electrical junction depth and compared to the metallurgical junction depth from SIMS analysis.     

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V_ds of 5.0 V is suppressed, whereas the drain leakage current at V_ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.     

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.     

Physics of fluctuation processes in downscaled silicon MOSFETs

Physical mechanics of fluctuation processes in advanced submicron and decananometer MOSFETs (metal-oxide-semiconductor field-effect transistors) including the ultra-thin film SOI (siliconon-insulator) devices using strained silicon films are reviewed. The review is substantially based on the results obtained by the authors. It is shown that the following drastic changes occur in the nature and parameters of noise in such devices as a result of their downscaling when the gate oxide thickness and the channel length and width are decreased, the SOI substrates are used, the silicon film thickness is reduced, the film doping level is varied, the strained silicon films are employed, etc. Firstly, the Lorentzian components can appear in the current noise spectra. Those components are due to (i) electron tunneling from the valence band through the gate oxide in the SOI MOSFETs of a sufficiently thin gate oxide (LKE-Lorentzians); (ii) Nyquist fluctuations generated in the source and drain regions near the back Si/SiO₂ interface in the SOI MOSFETs (BGI Lorentzians); (iii) electron exchange between the channel and some single trap in the gate oxide of the transistors with sufficiently small length and width of the channel (RTS Lorentzians). Secondly, the 1/f-noise level can increase due to (i) the appearance of recombination processes near the Si/SiO₂ interface activated by the currents of electron tunneling from the valence band; (ii) an increase in the trap density in the gate oxide of the devices fabricated on the biaxially tensile-strained silicon films; (iii) the contribution of the 1/f fluctuations of the current flowing through the gate oxide as a result of electron tunneling from the conduction band. At the same time, the 1/f-noise level may decrease due to a decrease in the trap density in the gate oxide of the transistors fabricated on the uniaxially tensile-strained silicon films. Moreover, a 1/f ^1.7 component may appear in the noise spectra for the transistors of a sufficiently thin gate oxide, whose component is due to charge fluctuations on the defects located near the interface between the gate polysilicon and the gate oxide.     

High-temperature diffusion of phosphorus and boron in silicon via vacancies or via self-interstitials?

The paper re-examines the effect of oxidation on the diffusion of phosphorus and boron in silicon as well as recent results on redistribution phenomena of these dopants under irradiation and on the emitter-push effect. It is shown that at high temperatures phosphorus and boron diffuse via a defect mechanism involving silicon self-interstitials. These results support the view-point that self-interstitials are the dominating point defects in silicon under thermal equilibrium conditions. Possible generation mechanisms for the self-interstitial supersaturation causing the emitter-push effect are suggested.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

An analytical study of substrate current in submicron MOS devices

In the present communication we have tried to study the substrate current behavior in the sub-micron devices after solving the second order differential equation using appropriate boundary conditions. Simple and accurate models for maximum lateral field, drain saturation voltage and for ionization length have been developed. The simulation result of ionization length shows a good match with the known result. Analysis also shows that dominant contributor to the error in the ionization length is not only because of the excess saturated voltage but also due to the channel length and the gate to source voltage. For sub-micron devices the saturation region shifts towards the source for higher drain voltage and larger gate oxide thickness.Received: 27 September 2004, Published online: 26 November 2004PACS: 85.30.De Semiconductor-device characterization, design, and modeling - 85.30.Tv Field effect devices     

磷通过热生长二氧化硅层在硅中的扩散

用四探针测量薄层电导方法及阳极氧化去层技术,测定了磷在硅中扩散的具体分布,在恒表面浓度下,它们偏离余误差函数分布。如认为这是由于扩散系数是杂质浓度的函数,实验得到了当杂质浓度大于10¹⁹原子/厘米³时,扩散系数随杂质浓度增加而增大的强烈依赖关系。用同样方法测定了磷通过二氧化硅层后在硅中扩散的具体分布,研究了这些杂质分布的特性,实验表明,不同厚度的氧化层在1300℃高温下仍具有掩蔽效应,在完全掩蔽失效时间附近,杂质分布的共同特点是表面浓度较低(～10¹⁷原子/厘米³)、结较浅(～1微米)。对不同厚度的氧化层,经过足够的时间后,硅中表面浓度不受氧化层厚度的影响,而只由扩散源的蒸气压决定。磷通过氧化层后扩散的具体分布情况还与扩散源的性质、条件等密切相关。扩散过程中观察到的氧化层厚度增长有可能影响表面附近杂质的具体分布情况。