不同封装方式对肖特基二极管高频性能的影响

肖特基二极管是太赫兹接收机的关键器件,通过在高频下对不同封装形式的肖特基二极管进行建模仿真,研究不同封装方式对肖特基二极管性能的影响。首先通过建立肖特基二极管的仿真模型,在高频结构仿真软件HFSS中对肖特基二极管在0~120 GHz频段进行仿真,得到该肖特基二极管的S参数,并对S参数仿真结果和实测结果进行对比,证明了该二极管模型的准确性。然后分别建立肖特基二极管的普通封装模型和肖特基二极管的倒装芯片(flip-chip)封装模型,并对这两种封装模型进行仿真,得到其在两种不同封装结构下的S参数,进而对两种不同封装方式的S参数的-3 dB带宽以及相位一致性进行对比分析。最终,对应用于太赫兹波段的肖特基二极管由于封装不同而带来的带宽以及相位的区别及其成因进行分析,论证了flip-chip封装更适合应用于太赫兹波段的肖特基二极管,与普通封装相比,该封装在高频下对肖特基二极管的电性能有比较大的改进。     

太赫兹GaAs肖特基混频二极管高频特性分析

在太赫兹波段,存在几种新的高频效应会限制混频二极管的高频特性.应用热电子发射理论和隧道理论,研究了外延层肖特基二极管的高频特性,并以截止频率为品质因数对二极管进行优化设计.研究表明,当二极管工作频率大于等离子频率时,二极管相当于一个电容,失去了混频性能;提高基底掺杂浓度可以减小基底等离子共振效应;外延层等离子频率非常重要并且在研究外延层等离子共振效应时必须考虑传输时间效应;减小阳极直径、减小外延层厚度、提高外延层掺杂浓度可以提高二极管的工作频率.这对太赫兹波段室温混频器件的研制具有重要的参考价值.     

0.38 THz混频器关键器件设计和仿真优化

太赫兹混频器是太赫兹波收发系统中的关键器件,是将信号频率从一个量值变换为另一个量值的电路器件,其中肖特基二极管是太赫兹混频器中的核心器件,除了肖特基二极管以外,低频滤波器、本振端口等也属于太赫兹混频器中的关键器件。对0.38 THz混频器中的关键组件包括波导管、肖特基二极管、滤波器等在HFSS中进行了建模、仿真,最后通过对仿真结果的分析,实现了可以满足0.38 THz太赫兹混频器的各个关键模块的模型,通过这些模型实现了混频器整体的优化。     

0.38 THz混频器关键器件设计和仿真优化北大核心CSCD

太赫兹混频器是太赫兹波收发系统中的关键器件,是将信号频率从一个量值变换为另一个量值的电路器件,其中肖特基二极管是太赫兹混频器中的核心器件,除了肖特基二极管以外,低频滤波器、本振端口等也属于太赫兹混频器中的关键器件。对0.38THz混频器中的关键组件包括波导管、肖特基二极管、滤波器等在HFSS中进行了建模、仿真,最后通过对仿真结果的分析,实现了可以满足0.38THz太赫兹混频器的各个关键模块的模型,通过这些模型实现了混频器整体的优化。     

基于CSMRC结构和容性肖特基二极管的220GHz三倍频器

设计了基于容性肖特基二极管的220 GHz非平衡三倍频器。首先对容性肖特基二极管进行测试和关键参数提取,建立了肖特基二极管的等效电路模型,以此为基础进行三倍频电路设计;在倍频电路设计中通过引入紧凑悬置微带谐振单元(CSMRC)滤波结构来减小信号传输损耗;由于三倍频电路设计中难以实现全波阻抗匹配,因此采用了整体电路结构谐波平衡调匹配方法设计倍频电路,最后对制备出的倍频器进行测试和分析;实验测试结果表明：倍频器在213.1~221.6 GHz范围内输出功率大于10 mW,倍频效率大于5%,最高输出功率为18.7 mW@218.6 GHz,最高倍频效率为8.24%@217.9 GHz。     

基于Ritz-Galerkin方法的太赫兹二极管检波器非线性分析

肖特基二极管检波器是太赫兹ASK/OOK通信系统的关键器件之一, 为了更好地分析肖特基二极管检波器的非线性特性, 从检波器的电路模型出发, 基于Ritz-Galerkin方法, 建立了检波器非线性特性的理论分析模型。并利用模型对检波器输出信号强度和灵敏度作了理论预测, 表明该理论模型能够精确预测检波器的非线性特性。最后利用该理论模型研究了输入信号强度、负载阻抗和外界温度对0.34 THz肖特基二极管检波器非线性特性的影响。结果表明随着功率的增加, 检波器由平方率区渐变至线性区只在特定条件下才成立, 在实际条件下很容易出现高阶效应。     

基于Ritz-Galerkin方法的太赫兹二极管检波器非线性分析

肖特基二极管检波器是太赫兹ASK/OOK通信系统的关键器件之一, 为了更好地分析肖特基二极管检波器的非线性特性, 从检波器的电路模型出发, 基于Ritz-Galerkin方法, 建立了检波器非线性特性的理论分析模型。并利用模型对检波器输出信号强度和灵敏度作了理论预测, 表明该理论模型能够精确预测检波器的非线性特性。最后利用该理论模型研究了输入信号强度、负载阻抗和外界温度对0.34 THz肖特基二极管检波器非线性特性的影响。结果表明随着功率的增加, 检波器由平方率区渐变至线性区只在特定条件下才成立, 在实际条件下很容易出现高阶效应。     

沟槽形状对硅基沟槽式肖特基二极管电学特性的影响

随着对电子产品节能环保要求的提高,对广泛应用于电子产品的肖特基二极管电学性能的要求也越来越高.含金属-氧化物-半导体结构的沟槽式肖特基二极管(trench barrier Schottky diodes,TMBS)由于其优异的性能而备受青睐.沟槽结构对提高肖特基二极管性能起着至关重要的作用,但是关于沟槽形状对二极管电学性能的影响尚未见有深入的研究报道.本文提出了两种新型的沟槽结构——圆角沟槽和阶梯型沟槽.通过模拟研究发现,圆角沟槽与传统的直角沟槽TMBS器件相比,在维持同样的漏电流和正向导通电压的条件下,击穿电压可以提高15.8%.阶梯沟槽与传统直角沟槽TMBS器件相比,可以在击穿电压不减小的情况下,漏电降低35%,正向导通电压仅略有增加.这归结于圆角沟槽和阶梯沟槽对有源区内部电场强度分布的调节.     

静电放电对功率肖特基二极管I-V及低频噪声特性的影响

本文基于人体放电模型分别对肖特基势垒二极管的阴极和阳极进行同一电压脉冲下的多次放电, 利用热电子发射理论、1/f噪声的迁移率涨落模型和白噪声理论, 分别深入研究静电放电损伤对器件I-V和低频噪声的影响. 结果表明, 静电放电作用于肖特基二极管阴极时损伤更严重, 噪声参量变化率更大. 随着放电次数的增加, 正向特性无变化, 反向电流总体增大, 偶有减小; 而正向和反向 1/f噪声均增大. 鉴于噪声与应力条件下器件内部产生的缺陷与损伤有关, 且更敏感, 故可将低频噪声特性用作肖特基二极管的静电放电损伤灵敏表征工具.     

不同位置二极管串并联方式对射频电路的影响

分析了单支肖特基二极管以及串并联模拟预失真电路的幅度和相位的非线性特性,仿真结果表明可以将二极管作为模拟预失真电路可调节的核心器件。利用传输矩阵分析得出改变肖特基二极管在预失真电路的不同位置,及不同的串并联连接方式,可以使幅度相位补偿曲线得到改善。由仿真结果可以看出,在不同位置以串联或并联的形式在电路中连接二极管,可有效改变曲线的位置和斜率,从而得到理想的目标曲线形状。     

Characterization of ion-implanted 4H-SiC Schottky barrier diodes

Ion-implantation layers are fabricated by multiple nitrogen ion-implantations (3 times for sample A and 4 times for sample B) into a p-type 4H-SiC epitaxial layer. The implantation depth profiles are calculated by using the Monte Carlo simulator TRIM. The fabrication process and the I--V and C--V characteristics of the lateral Ti/4H-SiC Schottky barrier diodes (SBDs) fabricated on these multiple box-like ion-implantation layers are presented in detail. Measurements of the reverse I--V characteristics demonstrate a low reverse current, which is good enough for many SiC-based devices such as SiC metal--semiconductor field-effect transistors (MESFETs), and SiC static induction transistors (SITs). The parameters of the diodes are extracted from the forward I--V and C--V characteristics. The values of ideality factor n of SBDs for samples A and B are 3.0 and 3.5 respectively, and the values of series resistance R_\rm s are 11.9 and 1.0~kΩ respectively. The values of barrier height φ _\rm B of Ti/4H-SiC are 0.95 and 0.72 eV obtained by the I--V method and 1.14 and 0.93 eV obtained by the C--V method for samples A and B respectively. The activation rates for the implanted nitrogen ions of samples A and B are 2\% and 4\% respectively extracted from C--V testing results.     

High-temperature current conduction through three kinds of Schottky diodes

Fundamentals of the Schottky contacts and the high-temperature current conduction through three kinds of Schottky diodes are studied. N-Si Schottky diodes, GaN Schottky diodes and AlGaN/GaN Schottky diodes are investigated by I--V--T measurements ranging from 300 to 523~K. For these Schottky diodes, a rise in temperature is accompanied with an increase in barrier height and a reduction in ideality factor. Mechanisms are suggested, including thermionic emission, field emission, trap-assisted tunnelling and so on. The most remarkable finding in the present paper is that these three kinds of Schottky diodes are revealed to have different behaviours of high-temperature reverse currents. For the n-Si Schottky diode, a rise in temperature is accompanied by an increase in reverse current. The reverse current of the GaN Schottky diode decreases first and then increases with rising temperature. The AlGaN/GaN Schottky diode has a trend opposite to that of the GaN Schottky diode, and the dominant mechanisms are the effects of the piezoelectric polarization field and variation of two-dimensional electron gas charge density.     

Fabrication and characteristics of lateral Ti/4H-SiC Schottky barrier diodes

This paper describes the fabrication and characteristics of the lateral Ti/4H-SiC Schottky barrier diodes (SBDs). SBDs are fabricated by nitrogen ion implantation into p-type 4H-SiC epitaxial layer. The implant depth profile is simulated using the Monte Carlo simulator TRIM. Measurements of the reverse I－V characteristics demonstrate a low reverse current, that is good enough for many SiC-based devices such as SiC metal-semiconductor field-effect transistors, and SiC static induction transistors. The parameters of the diodes are extracted from the forward I－V characteristics. The barrier height φ_b of Ti/4H-SiC is 0.95 eV.     

Breakdown characteristics of AIGaN/GaN Schottky barrier diodes fabricated on a silicon substrate

In this work, the breakdown characteristics of AlGaN/GaN planar Schottky barrier diodes （SBDs） fabricated on the silicon substrate are investigated. The breakdown voltage （BV） of the SBDs first increases as a function of the anodeto-cathode distance and then tends to saturate at larger inter-electrode spacing. The saturation behavior of the BV is likely caused by the vertical breakdown through the intrinsic GaN buffer layer on silicon, which is supported by the post-breakdown primary leakage path analysis with the emission microscopy. Surface passivation and field plate termination are found effective to suppress the leakage current and enhance the BV of the SBDs. A high BV of 601 V is obtained with a low on-resistance of 3.15 mΩ·cm^2.     

Breakdown characteristics of AlGaN/GaN Schottky barrier diodes fabricated on a silicon substrate

In this work, the breakdown characteristics of AlGaN/GaN planar Schottky barrier diodes(SBDs) fabricated on the silicon substrate are investigated. The breakdown voltage(BV) of the SBDs first increases as a function of the anodeto-cathode distance and then tends to saturate at larger inter-electrode spacing. The saturation behavior of the BV is likely caused by the vertical breakdown through the intrinsic GaN buffer layer on silicon, which is supported by the postbreakdown primary leakage path analysis with the emission microscopy. Surface passivation and field plate termination are found effective to suppress the leakage current and enhance the BV of the SBDs. A high BV of 601 V is obtained with a low on-resistance of 3.15 mΩ·cm2.     

Effect of diode size and series resistance on barrier height and ideality factor in nearly ideal Au/n type-GaAs micro Schottky contact diodes

Small high-quality Au/n type-GaAs Schottky barrier diodes (SBDs) with low reverse leakage current are produced using lithography. Their effective barrier heights (BHs) and ideality factors from current-voltage (I-V) characteristics are measured by a Pico ampere meter and home-built I-V instrument. In spite of the identical preparation of the diodes there is a diode-to-diode variation in ideality factor and barrier height parameters. Measurement of topology of a surface of a thin metal film with atomic force microscope (AFM) shows that Au-n type-GaAS SD consists of a set of parallel-connected micro and nanocontacts diodes with sizes approximately in a range of 100-200 nm. Between barrier height and ideality factor there is an inversely proportional dependency. With the diameter of contact increasing from 5 μm up to 200 μm, the barrier height increases from 0.833 up to 0.933 eV and its ideality factor decreases from 1.11 down to 1.006. These dependencies show the reduction of the contribution of the peripheral current with the diameter of contact increasing. We find the effect of series resistance on barrier height and ideality factor.