Novel offset gated poly-Si TFTs with subgate

We have fabricated a new offset gated poly-Si TFT by employing photoresist reflow, have measured various experimental data of the new device, such as hydrogenation results and high-frequency characteristics, and have analyzed device characteristics as a function of driving frequency. Our devices have a unique gate pattern and the hydrogenation effect is somewhat different from the previous results. Our experimental results suggest that with the same offset length, the device with a wider space between the maingate and the subgate is more advantageous for hydrogenation. Experimental results show that the leakage current of the new device is two orders of magnitude lower than that of the nonoffset gated device, while the ON current of the new device is almost identical to the nonoffset gated device in the typically used frequency range (10-100 kHz)     

High-performance poly-Si TFTs with ECR-plasma hydrogen passivation

High-performance thin-film transistors (TFTs) with electron-cyclotron resonance (ECR) plasma hydrogen passivation fabricated by the use of laser-recrystallized multiple-strip-structure poly-Si film are discussed. These TFTs have n-channel enhancement-mode characteristics with a large transconductance, a high switching ratio, and a threshold voltage as low as 0.4 v. The ECR-plasma hydrogen passivation of laser-recrystallized poly-Si, reduces the trap density of poly-Si and increases the carrier mobility thus, desirable TFT characteristics are obtained. This passivation increased the transconductance (g_m) of a TFT and decreased the leakage current between the source and the drain. As a result, a switching ratio as high as 2.5×10⁹ and very low leakage current of the order of 10¹⁴ A can be achieved by these high-performance TFTs     

Improved lifetime of poly-Si TFTs with a self-alignedgate-overlapped LDD structure

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H₂ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation     

High-performance RSD poly-Si TFTs with a new ONO gate dielectric

This paper developed a novel polycrystalline silicon (poly-Si) thin-film transistor (TFT) structure with the following special features: 1) a new oxide-nitride-oxynitride (ONO) multilayer gate dielectric to reduce leakage current, improved breakdown characteristics, and enhanced reliability; and 2) raised source/drain (RSD) structure to reduce series resistance. These features were used to fabricate high-performance RSD-TFTs with ONO gate dielectric. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time dependent dielectric breakdown, larger Q/sub BD/, and a lower charge-trapping rate than single-layer plasma-enhanced chemical vapor deposition tetraethooxysilane oxide or nitride. The fabricated RSD-TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 320 cm/sup 2//V/spl middot/s, and an on/off current ratio exceeding 10/sup 8/.     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

Performance of poly-Si TFTs fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.     

High-mobility poly-Si TFTs fabricated on flexible stainless-steelsubstrates

High mobility polycrystalline Si thin-film transistors (poly-Si TFTs) are firstly fabricated on flexible stainless-steel substrates 100 μm thick through low-temperature processes where both active Si and gate SiO₂ films are deposited by glow-discharge sputtering and the Si films are crystallized by KrF excimer laser irradiation. The gate SiO₂ films are sputter-deposited in oxygen atmosphere from the SiO₂ target. Resulting poly-Si TFTs show excellent characteristics of mobility of 106 cm²/V·s and drain current on-off ratio of as high as 1×10⁶. Thus, the poly-Si TFTs are very promising for realizing novel flat panel displays of lightweight and rugged LCDs and LEDs     

Electrical characteristics of MILC poly-Si TFTs with long Ni-offset structure

We have observed that B/sub 2/H/sub 6/-doped amorphous silicon (a-Si) showed a faster growth rate of metal-induced lateral crystallization (MILC) than that of undoped a-Si. From the analysis of the microstructure, it was thought that boron atoms could help modify the growth behavior from that of a branched crystal network to unidirectional crystal growth with few branches and that growth rate could to be enhanced. By using this good crystalline structure at the boundary region between the source/drain and channel, we have successfully fabricated p-type poly-Si thin-film transistors with good electrical properties with a MILC process.     

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.     

High performance low-temperature poly-Si n-channel TFTs for LCD

High-performance poly-Si TFTs were fabricated by a low-temperature 600°C process utilizing hard glass substrates. To achieve low threshold voltage (V_TH) and high field-effect mobility (μ_FE), the conditions for low-pressure chemical vapor deposition of the active layer poly-Si were optimized. Effective hydrogenation was studied using a multigate (maximum ten divisions) and thin-poly-Si-gate TFTs. The crystallinity of poly-Si after thermal annealing at 600°C depended strongly on the poly-Si deposition temperature and was maximum at 550-560°C. The V_TH and μ_FE showed a minimum and a maximum, respectively, at that poly-Si deposition temperature. The TFTs with poly-Si deposited at 500°C and a 1000-Å gate had a V _TH of 6.2 V and μ_FE of 37 cm²/V-s. The high-speed operation of an enhancement-enhancement type ring oscillator showed its applicability to logic circuits. The TFTs were successfully applied to 3.3-in.-diagonal LCDs with integration of scan and data drive circuits     

High-performance low-temperature poly-Si TFTs crystallized byexcimer laser irradiation with recessed-channel structure

High-performance low-temperature poly-Si (LTPS) thin-film transistors (TFTs) have been fabricated by excimer laser crystallization (ELC) with a recessed-channel (RC) structure. The TFTs made by this method possessed large longitudinal grains in the channel regions, therefore, they exhibited better electrical characteristics as compared with the conventional ones. An average field-effect mobility above 300 cm²/V-s and on/off current ratio higher than 10⁹ were achieved in these RC-structure devices. In addition, since grain growth could be artificially controlled by this method, the device electrical characteristics were less sensitive to laser energy density variation, and therefore the uniformity of device performance could be improved     

MONOS memory in sequential laterally solidified low-temperature poly-Si TFTs

A metal-oxide-nitride-oxide-polysilicon (MONOS) memory device fabricated by sequential lateral solidified (SLS) low-temperature polycrystalline silicon (poly-Si) technology on a glass substrate was investigated. The Si protrusions at grain boundaries (GBs) as a result of the SLS process can be well controlled and located along the width direction of the transistor. Protrusions at the GBs are utilized as emitting source to achieve a MONOS memory device with low operation voltage (/spl les/ 20 V), fast program/erase time, and wide V/sub th/ window by field-enhanced channel hot electron injection for programming and field-enhanced band-to-band tunneling-induced hot hole injection for erase. This is the first study to demonstrate a nonvolatile memory device in low-temperature poly-Si thin-film transistor (LTPS TFT) technology, which can be integrated with TFT-liquid crystal display, to reduce power consumption for mobile applications.     

High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable "mother" substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.     

Characteristics of low-temperature poly-Si TFTs on Al/glasssubstrates

The low-temperature poly-Si TFTs described here were fabricated on the Al/glass substrates by anodic oxidation of Al. An Al layer on glass substrates can be used to control threshold voltage, improve stabilities, and suppress the temperature rise due to self-heating. The Al layer on glass, thus assuring the improved reliability of displays, using this type of TFT, effectively suppressed the self-heating effect of poly-Si TFTs on glass. The threshold voltage of a TFT with an Al layer was more stable than that without an Al layer. These results were supported by numerical analysis     

A novel process-compatible fluorination technique with electrical characteristic improvements of poly-Si TFTs

A process-compatible fluorine passivation technique of poly-Si thin-film transistors (TFTs) was demonstrated by employing a novel CF/sub 4/ plasma treatment. Introducing fluorine atoms into poly-Si films can effectively passivate the trap states near the SiO/sub 2//poly-Si interface. With fluorine incorporation, the electrical characteristics of poly-Si TFTs can be significantly improved including a steeper subthreshold slope, smaller threshold voltage, lower leakage current, higher field-effect mobility, and better on/off current ratio. Furthermore, the CF/sub 4/ plasma treatment also improves the reliability of poly-Si TFTs with respect to hot-carrier stress, which is due to the formation of strong Si-F bonds.     

A source-follower type analog buffer using poly-Si TFTs with large design windows

New simple source follower circuits using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) as analog buffers for the integrated data driver circuit of active-matrix liquid crystal displays and active-matrix light emitting diodes are discussed. In addition to the threshold voltage difference of driving TFTs, the unsaturated of output voltage arisen from the significant subthreshold current will also result in the difficulty of the buffer circuit design. The proposed circuit is capable of minimizing the variation from both the signal timing and the device characteristics.     

Performance and reliability of poly-Si TFTs on FSG buffer layer

A novel and process-compatible scheme for fabricating poly-Si thin-film transistors (TFTs) on an FSG buffer layer was proposed and demonstrated. Experimental results reveal that remarkably improved device performance and uniformity can be achieved with appropriate fluorine concentration. The poly-Si TFTs fabricated on FSG layers have a higher on-current, a lower leakage current, and a higher field-effect mobility compared with the conventional poly-Si TFTs. Furthermore, the incorporation of fluorine also increased the reliability of poly-Si TFTs against hot carrier stressing, which is attributed to the formation of Si-F bonds.     

Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC

The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this letter. Experimental results have shown that fluorine ion implantation effectively minimized the trap state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, and high ON/OFF current ratio. Furthermore, the fluorine ions tended to segregate at the interface between the gate oxide and poly-Si layers during the excimer laser annealing, even without the extra deposition of pad oxide on the poly-Si film. The presence of fluorine obviously enhanced electrical reliability of poly-Si TFTs.     

High-performance poly-Si TFTs with fully Ni-self-aligned silicided S/D and gate structure

In this letter, fully Ni self-aligned silicided (fully Ni-salicided) source/drain (S/D) and gate polycrystalline silicon thin-film transistors (FSA-TFTs) have been successfully fabricated on a 40-nm-thick channel layer. Experimental results show that the FSA-TFTs give increased ON/OFF current ratio, improved subthreshold characteristics, less threshold voltage rolloff, and larger field-effect mobility compared with conventional TFTs. The FSA-TFTs exhibit small S/D and gate parasitic resistance and effectively suppress the floating-body effect and parasitic bipolar junction transistor action. The characteristics of the FSA-TFTs are suitable for high-performance driving TFTs with good output characteristics and large breakdown voltage.