Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I_on), off-current (I_off), subthreshold swing (S), and I_on/I_off ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (f_T) and maximum oscillation frequency (f_max) on gate–drain capacitance (C_gd) with the underlapping were investigated as the gate length (L_gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

InGaAs/InP heterojunction-channel tunneling field-effect transistor for ultra-low operating and standby power application below supply voltage of 0.5 V

An In_0.53Ga_0.47As/InP heterojunction-channel tunneling field-effect transistor (TFET) with enhanced subthreshold swing (S) and on/off current ratio (I_on/I_off) is studied. The proposed TFET achieves remarkable characteristics including S of 16.5 mV/dec, on-state current (I_on) of 421 μA/μm, I_on/I_off of 1.2 × 10¹² by design optimization in doping type of In_0.53Ga_0.47As channel at low gate (V_GS) and drain voltages (V_DS) of 0.5 V. Comparable performances are maintained at V_DS below 0.5 V. Moreover, an extremely fast switching below 100 fs is accomplished by the device. It is confirmed that the proposed TFET has strong potentials for the ultra-low operating power and high-speed electron device.     

Design and analysis of Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET)

In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III–V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t_epi) and height of source region (H_source) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I_on) of 694 μA/μm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (V_t) of 0.1 V, current gain cut-off frequency (f_T) of 12 GHz, and maximum oscillation frequency (f_max) of 283 GHz.     

Chemical bath deposition of CdS channel layer for fabrication of low temperature-processed thin-film-transistors

～66 nm thick CdS film with a hexagonal structure was uniformly generated via a low temperature-processed chemical bath deposition at 80 °C using a complexing agent of ethylenediaminetetraacetic acid and its crystal structure, surface morphology, optical transmittance, and Raman scattering property were measured. Grown CdS film was used as a channel layer for the fabrication of bottom-gate, top-contact thin-film-transistor (TFT). The TFT device with 60 °C-dried channel layer exhibited a poor electrical performance of on-to-off drain current ratio (I_on/I_off) of 5.1 × 10³ and saturated channel mobility (μ_sat) of 0.10 cm²/Vs. However, upon annealing at 350 °C, substantially improved electrical characteristics resulted, showing I_on/I_off of 5.9 × 10⁷ and μ_sat of 5.07 cm²/Vs. Furthermore, CdS channel layer was chemically deposited in an identical way on a transparent substrate of SiN_x/ITO/glass as part of transparent TFT fabrication, resulting in I_on/I_off of 5.8 × 10⁷ and μ_sat of 2.50 cm²/Vs.     

Thin film transistors based on TiO2 fabricated by using radio-frequency magnetron sputtering

This study demonstrates that nanocrystalline TiO₂ thin films were deposited on ITO/glass substrate by radio-frequency magnetron sputtering. Field-emission scanning electron microscope (FE-SEM) and atomic force microscopic (AFM) images showed the morphology of TiO₂ channel layer with grain size and root-mean-square (RMS) roughness of 15 and 5.39 nm, respectively. TiO₂ thin-film transistors (TFTs) with sputter-SiO₂ gate dielectric layer were also fabricated. It was found that the devices exhibited enhancement mode characteristics with the threshold voltage of 7.5 V. With 8-μm gate length, it was also found that the I_on/off ratio and off-state current were around 1.45×10² and 10 nA, respectively.     

Fabrication of thin-film transistor based on self-assembled single-walled carbon nanotube network

Thin-film transistor based on controllable electrostatic self-assembled monolayer single-wall carbon nanotubes (SWNTs) network has been fabricated by varying the density of nanotubes on the silicon substrate. The densities of SWNTs network have been investigated as a function of concentration and assembly time. It has been observed that the density of SWNTs network increases from 0.6 µm⁻² to 2.1 µm⁻², as the average on-state current (I_on) increases from 0.5 mA to 1.47 mA. The device has a current on/off ratio (I_on/I_off) of 1.3×10⁴ when I_on reaches to 1.34 mA.     

The effect of post-metal annealing on the electrical performance and stability of two-step-annealed solution-processed In2O3 thin film transistors

In this work, solution-processed indium oxide (In₂O₃) thin film transistors (TFTs) were fabricated by a two-step annealing method. The influence of post-metal annealing (PMA) temperatures on the electrical performance and stability is studied. With the increase of PMA temperatures, the on-state current and off-state current (I_on/I_off) ratio is improved and the sub-threshold swing (SS) decreased. Moreover, the stability of In₂O₃ TFTs is also improved. In all, In₂O₃ TFT with post-metal annealing temperature of 350°С exhibits the best performance (a threshold voltage of 4.75 V, a mobility of 13.8 cm²/V, an I_on/I_off ratio of 1.8 × 10⁶, and a SS of 0.76 V/decade). Meanwhile, the stability under temperature stress (TBS) and positive bias stress (PBS) also show a good improvement. It shows that the PMA treatment can effectively suppress the interface trap and bulk trap and result in an obviously improvement of the In₂O₃ TFTs performance.     

Top-gate amorphous IGZO thin-film transistors with a SiO buffer layer inserted between active channel layer and gate insulator

In this paper, top-gate thin-film transistors (TFTs) using amorphous In-Ga-Zn-O as the n-channel active layer and SiO₂ as gate insulator were fabricated by radio frequency magnetron sputtering at room temperature. In this device, a SiO layer was used to be a buffer layer between active layer and gate insulator for preventing the damage of the InGaZnO surface by the process of sputtering SiO₂ with relatively high sputtering power. The thickness of buffer layers was studied and optimized for enhancing the TFTs performances. Contrasting to the TFTs without buffer layer, the optimized thickness of 10 nm SiO buffer layer improved the top-gate TFTs performances greatly: mobility increases 30%, reached 1.29 cm²/V s, the I_on/I_off ratio increases 3 orders, and the trap density at the interface of channel/insulator decreases about 1 order, indicated that the improvement of semiconductor/dielectric interface by buffering the sputtering power.     

Electric-field induced ion-leveraged metal–insulator transition in conducting polymer-based field effect devices

The field effect devices prepared completely from conducting polymers, especially poly(3,4-ethylenedioxythiophene)/poly(styrene sulfonic acid) (PEDOT/PSS), were studied. Normally in a conductive “on” state, the transistor-like device has a transition to a substantially less conductive “off” state at an applied positive gate voltage, typically ∼15–25 V. The current ratio I_off/I_on can exceed 10⁻⁴ at room temperature. We have found that the field effect is strongly temperature dependent and is substantially reduced upon decreasing the temperature by only a 10 °C. This loss of current reduction upon application of a gate voltage is not due to the temperature dependence of the electrical conductivity of polymers of which the devices are made. The temperature dependence of the dc conductivity of the PEDOT/PSS follows the variable range hopping law both before and after application of the gate voltage, though with an increased activation energy, T₀. We suggest that the conducting polymer is near the metal–insulator transition and that the field effect in the device is related to the electric field modulating this transition in the region underneath the gate electrode. The transition is controlled and leveraged by ion motion. The time dynamics of the current with the gate modulation strongly supports our conjecture. We demonstrate the generality of the phenomena by presenting similar results for devices fabricated from the conducting polypyrrole doped with Cl.     

Mössbauer and XRD study of pulse plated Fe–P and Fe–Ni thin layers

⁵⁷Fe conversion electron Mössbauer spectroscopy, X-ray diffraction, electrochemical and magnetic measurements were used to study pulse electroplated Fe–P and Ni–Fe coatings. XRD and ⁵⁷Fe CEMS measurements revealed the amorphous character of the novel pulse plated Fe–P alloys. CEM spectra indicated significant differences in the short range order and in the magnetic anisotropy between the Fe–P deposits pulse plated at medium long deposition time (t _on?=?2 ms), with short relaxation time (t _off?=?9 ms) and low current density (I _p?=?0.05 Acm^?2) or at short deposition time (t _on?=?1 ms) with long relaxation time (t _off?=?250 ms) and high current density (I _p?=?1.0 Acm^?2). The broad peaks centred around the fcc reflections in XRD of the pulse plated Ni-22 wt.% Fe deposit reflected a microcrystalline Ni–Fe alloy with a very fine, 5–8 nm, grain size. The CEM spectrum of the pulse plated Ni-22 wt.% Fe coating corresponded to a highly disordered solid solution alloy containing a minute amount of ferrihydrite. Extreme favourable soft magnetic properties were observed with these Ni–Fe and Fe–P pulse plated thin layers.     

Extended-source broken gate tunnel FET for improving direct current and analog/radio-frequency performance

The various advantages of extended-source(ES), broken gate(BG), and hetero-gate-dielectric(HGD) technology are blended together for the proposed tunnel field-effect transistor(ESBG TFET) in order to enhance the direct-current and analog/radio-frequency performance. The source of the ESBG TFET is extended into channel for the purpose of increasing the point and line tunneling in the device at the tunneling junction, and then, the on-state current for the ESBG TFET increases. The influence of the source region length on the direct-current and radio-frequency performance parameters of the ESBG TFET is analyzed in detail. The results show that the proposed TFET exhibits a high on-state current to off-state current ratio of 1013, large transconductance of 1200 μS/μm, high cut-off frequency of 72.8 GHz, and high gain bandwidth product of 14.3 GHz. Apart from these parameters, the ESBG TFET also demonstrates high linearity distortion parameters in terms of the second-and third-order voltage intercept points, the third-order input interception point, and the third-order intermodulation distortion. Therefore, the ESBG TFET greatly promotes the application potential of conventional TFETs.     

Low voltage organic field effect transistors with a poly(hexylthiophene)–ZnO nanoparticles composite as channel material

We report on solution processable organic field effect transistors prepared using a poly(3‐hexylthiophene)–ZnO nanoparticles composite as channel semiconductor material and cross‐linked polyvinyl alcohol as gate insulator. Our transistors show a field effect mobility of 0.35 ± 0.06 cm²/V s, threshold voltage of –1.30 ± 0.11 V, and I_on/I_off ratio of (1.0 ± 0.1) × 10³. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application

In this paper, a gate-all-around junctionless tunnel field effect transistor (JLTFET) based on heterostructure of compound and group III–V semiconductors is introduced and simulated. In order to blend the high tunneling efficiency of narrow band gap material JLTFETs and the high electron mobility of III–V JLTFETs, a type I heterostructure junctionless TFET adopting Ge–Al _x Ga_1?x As–Ge system has been optimized by numerical simulation in terms of aluminum (Al) composition. To improve device performance, we considered a nanowire structure, and it was illustrated that high-performance logic technology can be achieved by the proposed device. The optimal Al composition founded to be around 20 % (x = 0.2). The numerical simulation results demonstrate that the proposed device has low leakage current I _OFF of ~1.9 × 10^?17, I _ON of 4 µA/µm, I _ON/I _OFF current ratio of 1.7 × 10¹¹ and subthreshold swing SS of 12.6 mV/decade at the 40 nm gate length and temperature of 300 K.     

Gadolinium scandate as an alternative gate dielectric in field effect transistors on conventional and strained silicon

Long channel n-type metal oxide semiconductor field effect transistors on thin conventional and strained silicon on insulator substrates have been prepared by integrating gadolinium scandate as high-κ gate dielectric in a gate last process. The GdScO₃ films were deposited by electron beam evaporation and subsequently annealed in oxygen atmosphere. Electrical characterization of readily processed devices reveals well behaved output and transfer characteristics with high I _on/I _off ratios of 10⁶–10⁸, and steep inverse subthreshold slopes down to 66 mV/dec. Carrier mobilities of 155 cm²/Vs for the conventional and 366 cm²/Vs for the strained silicon substrates were determined.     

低栅极电压控制下带有phenyltrimethoxysilane单分子自组装层的有机薄膜晶体管场效应特性研究

制作了底栅极顶接触有机薄膜晶体管器件,60 nm的pentacene被用作有源层,120 nm热生长的SiO₂作为栅极绝缘层.通过采用不同自组装修饰材料对器件的有源层与栅极绝缘层之间的界面进行修饰,如octadecyltrichlorosilane （OTS）,phenyltrimethoxysilane （PhTMS）,来比较界面修饰层对器件性能的影响.同时对带有PhTMS修饰层的OTFTs器件低栅极电压调制下的场效应行为及其载流子的传输机理进行研究.结果得到,当|V 关键词： 有机薄膜晶体管 自组装单分子层 场效应迁移率 低栅极调制电压     

3D quantum mechanical simulation of square nanowire MOSFETs by using NEGF method

In order to investigate the specifications of nanoscale transistors, we have used a three dimensional (3D) quantum mechanical approach to simulate square cross section silicon nanowire (SNW) MOSFETs. A three dimensional simulation of silicon nanowire MOSFET based on self consistent solution of Poisson-Schrödinger equations is implemented. The quantum mechanical transport model of this work uses the non-equilibrium Green’s function (NEGF) formalism. First, we simulate a double-gate (DG) silicon nanowire MOSFET and compare the results with those obtained from nanoMOS simulation. We understand that when the transverse dimension of a DG nanowire is reduced to a few nanometers, quantum confinement in that direction becomes important and 3D Schrödinger equation must be solved. Second, we simulate gate-all-around (GAA) silicon nanowire MOSFETs with different shapes of gate. We have investigated GAA-SNW-MOSFET with an octagonal gate around the wire and found out it is more suitable than a conventional GAA MOSFET for its more I _on /I _off , less Drain-Induced-Barrier-Lowering (DIBL) and less subthreshold slope.     

Nanoscale SiGe-on-insulator (SGOI) MOSFET with graded doping channel for improving leakage current and hot-carrier degradation

A novel graded doping profile, for the first time is introduced for reliability improvement and leakage current reduction. The proposed structure is called graded doping channel SiGe-on-insulator (GDC-SGOI). The key idea in this work is to modify the electric field and band energy with novel doping distribution in the channel for improving leakage current and hot electron. Using two-dimensional two-carrier simulation we demonstrate that the GDC-SGOI shows lower electron temperature near the drain region in the channel in comparison with the conventional SGOI (C-SGOI) with uniform doping. On the other hand, short channel effects (SCEs) such as drain induced barrier lowering (DIBL) and threshold voltage roll-off improvement leads to leakage current reduction. DIBL decrement and less dependence of the threshold voltage and DIBL on channel length variation in the GDC-SGOI structure show SCEs suppression. Furthermore the on-off current ratio (I_on/I_off) in the GDC-SGOI is higher than that achieved from the C-SGOI. Therefore, the results show that the GDC-SGOI structure especially in low power and device reliability has excellent performance in comparison with the C-SGOI.     

Temperature-dependent current conduction mechanism and charge trapping in Ta2O5 RF-sputtered on GaN

A gallium nitride (GaN) based Metal-Oxide-Semiconductor (MOS) capacitor was fabricated using radio frequency (RF)-sputtered tantalum oxide (Ta₂O₅) as the high-k gate dielectric. Electrical characteristics of this capacitor were evaluated via capacitance–voltage (C–V), current–voltage (I–V), and interface trap density (D_it) measurements with emphasis on the substrate temperature dependence ranging from 25 °C to 200 °C. Charge trapping and conduction mechanism in Ta₂O₅ were investigated. The experimental results suggested that higher substrate temperature rendered higher oxide capacitance, reduced gate leakage current, and lowered mid-gap interface trap density at the expenses of high border traps and high fixed oxide charges. The gate leakage current through Ta₂O₅ was found to obey the Ohm's conduction at lower gate bias and the Poole–Frenkel conduction at higher gate bias.     

A comparative analysis of thin-film transistors using aligned and random-network carbon nanotubes

The purpose of this project is to investigate the characterization of carbon nanotube (CNT) thin-film transistors based on two solution-based fabrication methods: dielectrophoretic deposition of aligned CNTs and self-assembly of random-network CNTs. The electrical characteristics of aligned and random-network CNT transistors are studied comparatively. In particular, the selection effect of metallic and semiconducting CNTs in the dielectrophoresis process is evaluated experimentally by comparing the output characteristics of the two transistors. Our results demonstrate that the self-assembly method produces a stronger field effect with a much higher on/off ratio (I _on /I _off ). This phenomenon provides evidence that the metallic CNTs are more responsive to dielectrophoretic forces than their semiconducting counterparts under common deposition conditions. In addition, the nanotube–nanotube cross-junctions in random-network CNT films create additional energy barriers and result in a reduced electric current. Thus, additional consideration must be applied when using different fabrication methods in building CNT-based electronic devices.