Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process

ESD protection for radio frequency (RF) applications must deal with good ESD performance, minimum capacitance, zero series resistance and good capacitance linearity. In order to fulfill these requirements, different ESD protection strategies for RF applications have been investigated in a 0.18 μm CMOS process. This paper compares different ESD protection devices and shows that a suitable ESD performance target for RF applications (200 fF max, 2 kV HBM) can be reached with a diode network scheme. The optimization of the diodes is then a key point which is detailed. A trade-off has to be found between the ESD performance, the voltage drop during ESD and the parasitic capacitance. Poly as well as shallow trench isolation (STI) bounded diodes have been studied and it appears clearly that a solution based on poly bounded diodes is the best choice.     

Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5-μm BCD process

Gate-grounded N-channel MOSFET(GGNMOS) has been extensively used for on-chip electrostatic discharge(ESD)protection. However, the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect. In this paper, an enhanced GGNMOS with P-base layer(PB-NMOS) are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer. TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices. All devices are fabricated in a 0.5-μm BCD process and measured using the transmission line pulsing(TLP)tester. Compared with the conventional GGNMOS, the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart, which can be increased by 15.38%. Furthermore, the PB-NMOS type 3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.     

Hybrid phase-locked loop with fast locking time and low spur in a 0.18-μm CMOS process

We propose a novel hybrid phase-locked loop(PLL) architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator(VCO) and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor(CMOS) process with a total die area of1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than-73 dB with a reference frequency of10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.