超深亚微米PMOS器件的NBTI退化机理

对超深亚微米PMOS器件的负栅压温度不稳定性(NBTI)退化机理进行了研究.主要集中在对器件施加NBT和随后的PBT应力后器件阈值电压的漂移上.实验证明反型沟道中空穴在栅氧中的俘获以及氢分子在栅氧中的扩散是引起NBTI退化的主要原因.当应力条件变为PBT时，陷落的空穴可以快速退陷，但只有部分氢分子可以扩散回栅氧与衬底界面钝化硅悬挂键，这就导致了PBT条件下阈值电压只能部分恢复. 关键词： 超深亚微米PMOS器件 负偏压温度不稳定性 界面陷阱 氢气     

NBT导致的深亚微米PMOS器件退化与物理机理

研究了深亚微米PMOS器件在负偏压温度(negative bias temperature, NBT) 应力前后的电流电压特性随应力时间的退化，重点分析了NBT应力对PMOS器件阈值电压漂移的影响，通过实验证明了在栅氧化层和衬底界面附近的电化学反应和栅氧化层内与氢相关的元素的扩散，是PMOS器件中NBT效应产生的主要原因.指出NBT导致的PMOS器件退化依赖于反应机理和扩散机理两种机理的平衡. 关键词： 深亚微米PMOS器件 负偏压温度不稳定性 界面态 氧化层固定正电荷     

Degradation characteristics and mechanism of PMOSFETs under NBT--PBT--NBT stress

Degradation characteristics of PMOSFETs under negative bias temperature--positive bias temperature--negative bias temperature (NBT--PBT--NBT) stress conditions are investigated in this paper. It is found that for all device parameters, the threshold voltage has the largest shift under the first NBT stress condition. When the polarity of gate voltage is changed to positive, the shift of device parameters can be greatly recovered. However, this recovery is unstable. The more severe degradation appears soon after reapplication of NBT stress condition. The second NBT stress causes in linear drain current to degrade greatly, which is different from that of the first NBT stress. This more severe parameter shift results from the wear out of silicon substrate and oxide interface during the first NBT and PBT stress due to carrier trapping/detrapping and hydrogen related species diffusion.     

Study on the drain bias effect on negative bias temperature instability degradation of an ultra-short p-channel metal-oxide-semiconductor field-effect transistor

This paper studies the effect of drain bias on ultra-short p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) degradation during negative bias temperature (NBT) stress. When a relatively large gate voltage is applied, the degradation magnitude is much more than the drain voltage which is the same as the gate voltage supplied, and the time exponent gets larger than that of the NBT instability (NBTI). With decreasing drain voltage, the degradation magnitude and the time exponent all get smaller. At some values of the drain voltage, the degradation magnitude is even smaller than that of NBTI, and when the drain voltage gets small enough, the exhibition of degradation becomes very similar to the NBTI degradation. When a relatively large drain voltage is applied, with decreasing gate voltage, the degradation magnitude gets smaller. However, the time exponent becomes larger. With the help of electric field simulation, this paper concludes that the degradation magnitude is determined by the vertical electric field of the oxide, the amount of hot holes generated by the strong channel lateral electric field at the gate/drain overlap region, and the time exponent is mainly controlled by localized damage caused by the lateral electric field of the oxide in the gate/drain overlap region where hot carriers are produced.     

Actions of negative bias temperature instability (NBTI) and hot carriers in ultra-deep submicron p-channel metal——oxide——semiconductor field-effect transistors (PMOSFETs)

Hot carrier injection (HCI) at high temperatures and different values of gate bias V_g has been performed in order to study the actions of negative bias temperature instability (NBTI) and hot carriers. Hot-carrier-stress-induced damage at V_g=V_d, where V_d is the voltage of the transistor drain, increases as temperature rises, contrary to conventional hot carrier behaviour, which is identified as being related to the NBTI. A comparison between the actions of NBTI and hot carriers at low and high gate voltages shows that the damage behaviours are quite different: the low gate voltage stress results in an increase in transconductance, while the NBTI-dominated high gate voltage and high temperature stress causes a decrease in transconductance. It is concluded that this can be a major source of hot carrier damage at elevated temperatures and high gate voltage stressing of p-channel metal--oxide--semiconductor field-effect transistors (PMOSFETs). We demonstrate a novel mode of NBTI-enhanced hot carrier degradation in PMOSFETs. A novel method to decouple the actions of NBTI from that of hot carriers is also presented.     

Effect of substrate bias on negative bias temperature instability of ultra-deep sub-micro p-channel metal--oxide--semiconductor field-effect transistors

The effect of substrate bias on the degradation during applying a negative bias temperature (NBT) stress is studied in this paper. With a smaller gate voltage stress applied, the degradation of negative bias temperature instability (NBTI) is enhanced, and there comes forth an inflexion point. The degradation pace turns larger when the substrate bias is higher than the inflexion point. The substrate hot holes can be injected into oxide and generate additional oxide traps, inducing an inflexion phenomenon. When a constant substrate bias stress is applied, as the gate voltage stress increases, an inflexion comes into being also. The higher gate voltage causes the electrons to tunnel into the substrate from the poly, thereby generating the electron--hole pairs by impact ionization. The holes generated by impact ionization and the holes from the substrate all can be accelerated to high energies by the substrate bias. More additional oxide traps can be produced, and correspondingly, the degradation is strengthened by the substrate bias. The results of the alternate stress experiment show that the interface traps generated by the hot holes cannot be annealed, which is different from those generated by common holes.     

The study on mechanism and model of negative bias temperature instability degradation in P-channel metal-oxide-semiconductor field-effect transistors

Negative Bias Temperature Instability (NBTI) has become one of the most serious reliability problems of metal- oxide-semiconductor field-effect transistors (MOSFETs). The degradation mechanism and model of NBTI are studied in this paper. From the experimental results, the exponential value 0.25-0.5 which represents the relation of NBTI degradation and stress time is obtained. Based on the experimental results and existing model, the reaction-diffusion model with H+ related species generated is deduced, and the exponent 0.5 is obtained. The results suggest that there should be H+ generated in the NBTI degradation. With the real time method, the degradation with an exponent 0.5 appears clearly in drain current shift during the first seconds of stress and then verifies that H+ generated during NBTI stress.     

Effects of stress conditions on the generation of negative bias temperature instability-associated interface traps

The exponent n of the generation of an interface trap(Nit),which contributes to the power-law negative bias temperature instability(NBTI)degradation,and the exponent’s time evolution are investigated by simulations with varying the stress voltage Vgand temperature T.It is found that the exponent n in the diffusion-limited phase of the degradation process is irrelevant to both Vgand T.The time evolution of the exponent n is affected by the stress conditions,which is reflected in the shift of the onset of the diffusion-limited phase.According to the diffusion profiles,the generation of the atomic hydrogen species,which is equal to the buildup of Nit,is strongly correlated with the stress conditions,whereas the diffusion of the hydrogen species shows Vg-unaffected but T-affected relations through the normalized results.     

Evaluation of negative bias temperature instability in ultra-thin gate oxide pMOSFETs using a new on-line PDO method

A new on-line methodology is used to characterize the negative bias temperature instability (NBTI) without inherent recovery. Saturation drain voltage shift and mobility shift are extracted by I_D-V_D characterizations, which were measured before stress, and after every certain stress phase, using the proportional differential operator (PDO) method. The new on-line methodology avoids the mobility linearity assumption as compared with the previous on-the-fly method. It is found that both reaction--diffusion and charge-injection processes are important in NBTI effect under either DC or AC stress. A similar activation energy, 0.15 eV, occurred in both DC and AC NBTI processes. Also degradation rate factor is independent of temperature below 90\du\ and sharply increases above it. The frequency dependence of NBTI degradation shows that NBTI degradation is independent of frequencies. The carrier tunnelling and reaction--diffusion mechanisms exist simultaneously in NBTI degradation of sub-micron pMOSFETs, and the carrier tunnelling dominates the earlier NBTI stage and the reaction--diffusion mechanism follows when the generation rate of traps caused by carrier tunnelling reaches its maximum.     

On the effects of NBTI degradation in p-MOSFET devices

This paper presents the effects of interface trap concentration and threshold voltage shift on NBTI degradation in p-MOSFETs. To explore the degradation mechanisms, transistors having an EOT of 1.1 nm and 5 nm were simulated by applying various stress conditions. The NBTI degradation mechanism was studied by varying the gate voltage, temperature and substrate doping level. The simulations show NBTI degradation in terms of the threshold voltage shift, ΔV_th and number of interface traps, ΔN_it. The simulation results show an improved degradation trend in terms of ΔV_th and ΔN_it when the substrate doping level is increased.     

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability （NBTI） and stress-induced leakage current （SILC） both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts： the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.     

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.     

Study on the degradation of NMOSFETs with ultra-thin gate oxide under channel hot electron stress at high temperature

This paper studies the degradation of device parameters and that of stress induced leakage current (SILC) of thin tunnel gate oxide under channel hot electron (CHE) stress at high temperature by using n-channel metal oxide semiconductor field effect transistors (NMOSFETs) with 1.4-nm gate oxides. The degradation of device parameters under CHE stress exhibits saturating time dependence at high temperature. The emphasis of this paper is on SILC of an ultra-thin-gate-oxide under CHE stress at high temperature. Based on the experimental results, it is found that there is a linear correlation between SILC degradation and V_h degradation in NMOSFETs during CHE stress. A model of the combined effect of oxide trapped negative charges and interface traps is developed to explain the origin of SILC during CHE stress.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

具有HfN/HfO2栅结构的p型MOSFET中的负偏置-温度不稳定性研究

研究了HfN/HfO₂高K栅结构p型金属-氧化物-半导体(MOS)晶体管(MOSFET)中，负 偏置-温度应力引起的阈值电压不稳定性(NBTI)特征.HfN/HfO₂高K栅结构的等效 氧化层厚度(EOT)为1.3nm，内含原生缺陷密度较低.研究表明，由于所制备的HfN/HfO₂ 高K栅结构具有低的原生缺陷密度，因此在p-MOSFET器件中观察到的NBTI属HfN/HfO2高K栅结构的本征特征，而非工艺缺陷引起的；进一步研究表明，该HfN/HfO₂高K栅结构中观察到的NBTI与传统的SiO₂基栅介质p-MOSFET器件中观察 到的NBTI具有类似的特征，可以被所谓的反应-扩散(R-D)模型表征： HfN/HfO₂ 栅结构p-MOSFET器件的NBTI效应的起源可以归为衬底注入空穴诱导的界面反应机理，即在负 偏置和温度应力作用下，从Si衬底注入的空穴诱导了Si衬底界面Si-H键断裂这一化学反应的 发生，并由此产生了Si^＋陷阱在Si衬底界面的积累和H原子在介质层内部的扩散 ，这种Si^＋陷阱的界面积累和H原子的扩散导致了器件NBTI效应的发生. 关键词： 高K栅介质 负偏置-温度不稳定性(NBTI) 反应-扩散(R-D)模型     

Effects of DC and AC stress on the VT shift of AlGaN/GaN MIS-HEMTs

AlGaN/GaN MIS-HEMTs with adjusted V_T were fabricated using a recess gate to investigate the effect on actual operation when the polarity of the gate voltage is opposite in the on- and off-state. The direction and time exponents of V_T shift depend on the polarity of the gate bias stress. Electrons detrapping from the Al₂O₃/AlGaN interface trap site to AlGaN under negative gate bias stress has to overcome the energy barrier, resulting in a higher temperature dependence. In addition, the unaffected g_m and SS show that the degradation occurred primarily at the Al₂O₃/AlGaN interface rather than channel or mobility degradation. For unipolar and bipolar AC stresses, the time exponent of the V_T shift during stress time has two values, and a relatively low value during relaxation after bipolar AC stress. These results may be due to the further degradation by V_min at the broader energy levels of the Al₂O₃/AlGaN interface.     

Soft X-ray photoemission study of nitrogen diffusion in TiN/HfO:N gate stacks

The impact of HfO:N post nitridation anneal (PNA) and gate fabrication on the physico-chemical properties of the TiN/HfO:N/SiO₂/Si stack are investigated using Soft X-ray Photoelectron Spectroscopy (S-XPS) and Vacuum UltraViolet Spectroscopic Ellipsometry (VUV-SE). Defects created in the high-k during plasma nitridation are passivated by PNA under O₂. Both oxygen and nitrogen diffusion is observed towards the bottom SiO₂/Si interface together with a regrowth of the SiO₂. These defects play a major role regarding nitrogen diffusion during gate fabrication. Without PNA, no diffusion is observed because O and N atoms are trapped inside the high-k. With PNA and simultaneous defects passivation, nitrogen from both metal gate and high-k diffuses towards the bottom SiO₂/Si interface.     

高场应力及栅应力下AlGaN/GaN HEMT器件退化研究

采用不同的高场应力和栅应力对AlGaN/GaN HEMT器件进行直流应力测试,实验发现：应力后器件主要参数如饱和漏电流,跨导峰值和阈值电压等均发生了明显退化,而且这些退化还是可以完全恢复的;高场应力下,器件特性的退化随高场应力偏置电压的增加和应力时间的累积而增大;对于不同的栅应力,相对来说,脉冲栅应力和开态栅应力下器件特性的退化比关态栅应力下的退化大.对不同应力前后器件饱和漏电流,跨导峰值和阈值电压的分析表明,AlGaN势垒层陷阱俘获沟道热电子以及栅极电子在栅漏间电场的作用下填充虚栅中的表面态是这些不同应 关键词： AlGaN/GaN HEMT器件 表面态(虚栅) 势垒层陷阱 应力     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

超深亚微米PMOSFET的自愈合效应

主要研究负栅压偏置不稳定性(negative bias temperature instability，NBTI)效应中的自愈合效应，研究了器件阈值电压随着恢复时间和应力时间的恢复规律.研究表明器件的退化可以恢复是由于NBTI应力后界面态被氢钝化. 关键词： 负偏置温度不稳定性效应 自愈合效应 应力时间 PMOSFET