基于交通故障报警系统的组合逻辑电路的设计

用数字信号完成对数字量进行算术运算和逻辑运算的电路称为数字电路,可以分为组合逻辑电路和时序逻辑电路两大类.其中,组合逻辑电路是由最基本的逻辑门电路组合而成.文章以交通故障报警系统为例介绍了三种设计方案,以便学生熟悉常见组合逻辑电路的特点及应用.     

简单逻辑门电路学习方法初探

逻辑门是集成电路上的基本组件,逻辑门电路是当前数字电路广泛应用的重要前提和基础,它是不单是物理教育的重要组成部分,更是电子电器和计算机等相关专业的基础知识。由于逻辑电路要领功能繁多,记忆复杂,不易于掌握,学习起来容易感到力不从心。本文介绍了逻辑门电路的基本概念及表示方法,用类比的方法对逻辑门电路的规律进行总结,最后重点阐述逻辑门电路的实际应用。     

A comparative study on gate leakage and performance of high-𝛋 nano-CMOS logic gates

This paper provides a novel attempt to evaluate the gate leakage and delay characteristics of CMOS transistors and logic gates with various alternative high-κ gate dielectrics, which are replacing SiO₂ in traditional nanoscale MOSFETs. Results have been obtained for both fixed as well as variable loads. The assumption that all gates drive the same load is considered in order to provide a fair comparison of the effect of the variation of design and process parameters, especially that of different high-κ dielectrics on the gate direct tunnelling current and propagation delay. On the other hand, the variable loading effect considers a set of practical loading conditions for the logic gates. An exhaustive comparison of all cases finally presents concluding evidence that the tunnelling current is independent of the loading conditions. On the other hand, there is an increase in the delay as the dielectric constant of the gate material, and consequently the load on the device, increases. Ultimately, this paper presents fast and accurate models for on-the-fly calculation of tunnelling current and delay with the aim of integrating them into design automation tools.     

势阱离子+腔场系统中量子逻辑门的实现

基于光腔中的势阱离子同时与外激光场和腔场发生相互作用的特性，我们提出了一种量子逻辑门的实现方案。在该方案中，量子逻辑门是以离子内态和腔态作为比特，而势阱离子的运动态作为辅助比特始终保持在基态。而且，没有采用Lamb-Dicke近似，因而更容易为实验所实现。     

Bounds on the sizes of irredundant test sets and sequences for combinational logic networks

We present a method of determining lower and upper bounds on the number of tests required to detect all detectable faults in combinational logic networks. The networks are composed of AND, OR, NAND, NOR, and XOR gates. The fault model assumes that single stuck-at-zero faults occur on the lines of the networks, with the additional requirement that XOR gates be tested with all possible input combinations. The goal is to provide a simple and efficient implementation that processes the fanout-free subnetworks separately, and then combines the results without the need to consider the effects of reconvergent fanout. We introduce the concepts of irredundant test sets, where no test can be deleted regardless of the order of test application, and irredundant test sequences, where every test detects at least one additional fault when tests are applied in order. Identifying and differentiating between these types of collections of tests allows us to understand more precisely the mechanisms and expected performance of test generation and test compaction methods. We apply our test counting technique and two other published procedures to a set of benchmark circuits. Our bounds are shown to compare favorably to the results obtained by the other published approaches. We obtain minimal and maximal test sets and test sequences using a greedy optimization technique. Our bounds are shown to produce tight bounds for the smaller circuits; they grow more conservative as the size of the circuits increase.     

非可逆逻辑门的量子可逆实现研究

逻辑关系可用逻辑函数表示,量子逻辑关系是可逆的,引入和定义了量子逻辑函数;通过引入辅助量子位,增添量子输出信号的区分位,完成对非可逆逻辑门的改造,使非可逆逻辑门在量子电路中得到可逆实现,并研究了一些有用的非可逆逻辑门的改造方法,给出可实现的优化后的量子电路。     

基于标准单元库的多级函数分解

本文提出在ASIC综合技术中基于标准单元库的多级逻辑函数分解技术。分解过程利用单元库函数真值矩阵及各分解部分用标准单元实现的难易程度、逻辑级数来评价、引导分解得到的多级逻辑易于用标准单元组合实现。使用的标准单元类型具有较大程度的相似性,有利于基于标准单元布局布线软件进一步减少芯片面积。     

五种可预置数字均衡器CS7388电路的工作原理和测试方法简介

利用A370大规模集成电路测试系统，实现五种可预置数字均衡器CS7388电路的性能测试。