A generalized formula to determine the relaxation time distribution in dielectrics

The distribution of relaxation times is derived for dielectrics with constants featuring general functions in the - plane. A simple algorithm to determine the distribution parameters is also suggested. The algebraic method adopted enables translation of the algorithm into software to facilitate an efficient processing of data. The new distribution developed here could have an effective use in studies of dispersion in dielectrics and interfaces.     

Investigation of the low frequency dispersion of InP-oxide using a new Cole-Cole double-arc distribution

A new relaxation time distribution has been developed for double arc Cole-Cole plots in order to study the dispersion relation of InP-oxide. As suggested by a carrier injection model, the low frequency dispersion most likely originates from remaining In at the interface. The presence of In is a direct consequence of the Al electrode formation where the vapor-deposited electrode reacts with the InPO₄.     

The distribution of trapping states at the Al/InP-oxide interface

The volume density of trapping states is derived throughout the metal-dielectric interface. This has been facilitated by equating the dielectric loss component to the tunneling conductance using a new relaxation time formulation. Subsequently, the trap distribution at the Al/InPO₄ interface has featured a peak of 1.15×10¹⁹ cm^–3 at about 15 Å from the Al contacting electrode. The new approach could be extended to deal with semiconductor-dielectric interfaces.     

Dielectric and interfacial properties of InP plasma-grown oxides

Methods of dielectric analysis have been employed to investigate the frequency dispersion of InP-oxide dielectric in MOS and MOM devices. The Cole-Cole empirical method has indicated a wide range of relaxation time for the interfacial polarization. This has been interpreted in terms of a model of carrier injection from the gate metal into the oxide gap states. The model is proposed in conjunction with the anomalous hysteresis in the MOM C-V characteristics and could be applied to other MIS systems.Formerly with the department of Engineering, Cambridge University, U.K.     

Photoinjection studies of ion-implantation-induced electron traps in MOS structures

Trapping centers related to P⁺ and B⁺ ions implanted in the SiO₂ layer as well as traps introduced into SiO₂ during boron implantation through the oxide into the silicon substrate have been investigated. The internal photoemission method has been used to estimate their capture cross section and total densityN _t .     

Mechanism of conductivity in metal-polymer-metal structures

Received: 25 September 1998 / Accepted: 25 November 1998 / Published online: 24 February 1999     

A thin-film transistor with a very thin a-Si:H layer and its application for an LC panel

One of the disadvantages of applying an a-Si:H thin-film transistor (TFT) to an active matrix-addressed liquid crystal (LC) panel is that a TFT with an a-Si:H has a very large photo-leakage current because of the high photo-conductivity of an a-Si:H itself.We have tried decreasing the photo-leakage current by varying the thickness of an a-Si:H layer (L) in TFTs and investigated the characteristics of TFTs, mainly drain voltage versus drain current containing photo-leakage current (I _ph).As a result, it is shown that lnI _ph is proportional to InL, and its gradient is 1.5–2.0. We assume that the thinner an a-Si:H layer is, the more effective the recombination of carriers at the interface states is forI _ph.We have applied TFT with a very thin a-Si:H layer (30nm) to a full-color active matrix-addressed LC panel for a moving picture display and realized a display of good quality under illuminated condition of 5×10⁴lx without a shading layer in it.     

Study of HfSiO film prepared by electron beam evaporation for high-k gate dielectric applications

The purpose of this paper is to report some experimental results with HfSiO films formed on silicon substrates by electron beam evaporation (EB-PVD) and annealed at different temperatures. The images of atomic force microscope (AFM) indicated that HfSiO film annealed at 900 °C was still amorphous, with a surface roughness of 0.173 nm. X-ray photoelectron spectroscopy (XPS) analysis revealed that the chemical composition of the film was (HfO₂)₃(SiO₂) and Hf-Si-O bonds existed in the annealed film. Electrical measurements showed that the equivalent oxide thickness (EOT) was 4 nm, the dielectric constant was around 6, the breakdown voltage was 10 MV/cm, the fixed charge density was −1.2 × 10¹² cm⁻², and the leakage current was 0.4 μA/cm² at the gate bias of 2 V for 6 nm HfSiO film. The annealing after deposition effectively reduced trapping density and the leakage current, and eliminated hysteresis in the C-V curves. Annealing also induced SiO₂ growth at the interface.     

Thickness determination of thin and ultra-thin SiO2 films by C-AFM IV-spectroscopy

Conductive atomic force microscopy was used to determine the electrical oxide thickness for five different silicon dioxide layers with thickness in the order of 1.6-5.04 nm. The electrical thickness results were compared with values determined by ellipsometry. A semi-analytical tunnelling current model with one single parameter set was used to superpose current/voltage curves in both the direct tunnelling and the Fowler-Nordheim tunnelling regime regions. The overall electrical oxide thickness was determined by statistical means from results of nearly 3000 IV-curves recorded for different conductive CoCr-coated tips. Good agreement between the shape of model and experimental data was achieved, widely independent of the oxide thickness. Compared with the ellipsometry value, the electrical thickness was larger by a value of 0.36 nm (22%) for the thinnest oxide and smaller by a value of 0.31 nm (6%) for the thickest oxide, while intermediate values yielded differences better than 0.15 nm (<6%). The physical differences between the measurement techniques were shown to contribute to this observation. In addition, statistical deviations between single and multiple measurements using a single tip and using a number of different tips were analysed. The causes, for example, natural oxide thickness variations, tip wear, air humidity induced effects and contaminations, are evaluated and discussed. The method proposed was able to determine the electrical oxide thickness with a standard deviation in the order of ±6-9%. The results suggest that for optimal results it is necessary to perform several repetitions of IV-measurements for one sample and, in addition, to employ more than one tip.     

C-AFM-based thickness determination of thin and ultra-thin SiO2 films by use of different conductive-coated probe tips

The influence of the probe tip type on the electrical oxide thickness result was researched for four differently coated conductive tip types using SiO₂ (oxide) films with optical thickness of 1.7-8.3 nm. For this purpose, conductive atomic force microscopy (C-AFM) was used to measure more than 7200 current-voltage (IV) curves. The electrical oxide thickness was determined on a statistical basis from the IV-curves using a recently published tunnelling model for C-AFM application. The model includes parameters associated with the probe tip types used. The evolution of the tip parameters is described in detail. For the theoretical tip parameters, measured and calculated IV-curves showed excellent agreement and the electrical oxide thickness versus the optical oxide thickness showed congruent behaviour, independent of the tip type. However, differences in the electrical oxide thickness were observed for the different tip types. The theoretical parameters were modified experimentally in order to reduce these differences. Theoretical and experimental tip parameters were compared and their effect on the differences in the electrical oxide thickness is discussed for the different tip types. Overall, it is shown that the proposed model provides a comprehensive framework for determining the electrical oxide thickness using C-AFM, for a wide range of oxide thicknesses and for differently coated conductive tips.     

Microstructure and dielectric properties of La2O3 doped amorphous SiO2 films as gate dielectric material

As a potential gate dielectric material, the La₂O₃ doped SiO₂ (LSO, the mole ratio is about 1:5) films were fabricated on n-Si (0 0 1) substrates by using pulsed laser deposition technique. By virtue of several measurements, the microstructure and electrical properties of the LSO films were characterized. The LSO films keep the amorphous state up to a high annealing temperature of 800 °C. From HRTEM and XPS results, these La atoms of the LSO films do not react with silicon substrate to form any La-compound at interfacial layer. However, these O atoms of the LSO films diffuse from the film toward the silicon substrate so as to form a SiO₂ interfacial layer. The thickness of SiO₂ layer is only about two atomic layers. A possible explanation for interfacial reaction has been proposed. The scanning electron microscope image shows the surface of the amorphous LSO film very flat. The LSO film shows a dielectric constant of 12.8 at 1 MHz. For the LSO film with thickness of 3 nm, a small equivalent oxide thickness of 1.2 nm is obtained. The leakage current density of the LSO film is 1.54 × 10⁻⁴ A/cm² at a gate bias voltage of 1 V.     

Characteristics of sandwich-structured Al2O3/HfO2/Al2O3 gate dielectric films on ultra-thin silicon-on-insulator substrates

Sandwich-structure Al₂O₃/HfO₂/Al₂O₃ gate dielectric films were grown on ultra-thin silicon-on-insulator (SOI) substrates by vacuum electron beam evaporation (EB-PVD) method. AFM and TEM observations showed that the films remained amorphous even after post-annealing treatment at 950 °C with smooth surface and clean silicon interface. EDX- and XPS-analysis results revealed no silicate or silicide at the silicon interface. The equivalent oxide thickness was 3 nm and the dielectric constant was around 7.2, as determined by electrical measurements. A fixed charge density of 3 × 10¹⁰ cm⁻² and a leakage current of 5 × 10⁻⁷A/cm² at 2 V gate bias were achieved for Au/gate stack /Si/SiO₂/Si/Au MIS capacitors. Post-annealing treatment was found to effectively reduce trap density, but increase in annealing temperature did not made any significant difference in the electrical performance.     

Low field DC investigation of hot carrier trapping in silicon dioxide films

The experimental method used in this work is based upon the idea of nonavalanche injection of carriers heated by direct electric field. The structure consisted of an n-channel MOS transistor and two p-n junctions. The process of charge injection in this structure was investigated by studying the dependence of gate current on heating voltage. The trapping properties of the SiO₂ film were studied by monitoring the charging of the film during injection of electrons. The capture cross-sections, the trap centre concentrations and the dependence of the capture cross section on the electric field for fields between 1 MV/cm and 2.5 MV/cm were determined.     

The conductance and capacitance-frequency characteristics of Au/pyronine-B/p-type Si/Al contacts

The rectifying junction characteristics of the organic compound pyronine-B (PYR-B) film on a p-type Si substrate have been studied. The PYR-B has been evaporated onto the top of p-Si surface. The barrier height and ideality factor values of 0.67 ± 0.02 eV and 2.02 ± 0.03 for this structure have been obtained from the forward bias current-voltage (I-V) characteristics. The energy distribution of the interface states and their relaxation time have been determined from the forward bias capacitance-frequency and conductance-frequency characteristics in the energy range of ((0.42 ± 0.02) − E_v)-((0.66 ± 0.02) − E_v) eV. The interface state density values ranges from (4.21 ± 0.14) × 10¹³ to (3.82 ± 0.24) × 10¹³ cm⁻² eV⁻¹. Furthermore, the relaxation time ranges from (1.65 ± 0.23) × 10⁻⁵ to (8.12 ± 0.21) × 10⁻⁴ s and shows an exponential rise with bias from the top of the valance band towards the midgap.     

Core-electron binding energies in atoms and monolayers adsorbed on metallic substrates

A Born-Haber cycle analysis of photoemission from atoms and monolayers adsorbed on metallic surfaces elucidates the effects of the substrate on the initial and final state contributions to measured core-electron binding energies. For rare gases both a dependence on the work function of the substrate and on the final state screening energy are identified. Depending on the relative magnitudes of the work function of the substrate and the ionization potential of the core-ionized atom, the screening charge may reside either in the substrate or on the adsorbate atom itself. Within the monolayer range, the coverage-dependence of the core-electron binding energy is shown to be largely a final-state effect. The Born-Haber cycle relating the Auger decay energy of an adsorbed core-ionized atom to that of a similar free atom is also presented. These formulations are tested using data for Xe adsorbed on Pd and Cs.     

Constant schubweg for hole transport in corona charged fluorethylenepropylene

Thin (25 m) foils of Teflon^® FEP are charged positively in a constant-current corona triode with currents between 1–6×10^–9 A to a voltage of 3 kV. Experimental results give the voltage as a function of time during charging and during the discharge which occurs after the corona current has been turned off. Results can be interpreted in terms of a theory which introduces shallow surface and deep bulk traps and assumes that the field-induced carrier drift is characterized by a constant schubweg.     

A Novel Super-Junction Lateral Double-Diffused Metal--Oxide--Semiconductor Field Effect Transistor with n-Type Step Doping Buffer Layer

A novel super-junction lateral double-diffused metal-oxide--semiconductor field effect transistor （SJ-LDMOSFET） with n-type step doping buffer layer is proposed. The step doping buffer layer almost completely eliminates the substrate-assisted depletion effect, modulates lateral electric field and achieves nearly uniform surface field. On the other hand, the buffer layer also provides another conductive path and reduces on-state resistance. In short, the proposed LDMOSFET improves trade-off performance between breakdown voltage （B V） and specific on-state resistance Ron,sp. Compared with the conventional SJ-LDMOSFET, the simulation results indicate that the BV of the SSJ-LDMOSFET is increased from saturation voltage 121.7V to 644.9 V; at the same time, the specific on-state resistance is decreased from 0.314 Ω.cm^2 to 0.14 Ω.cm^2 by virtue of 3D numerical simulations using ISE when the drift region length and the step number are taken as 48μm and 3, respectively.     

Tunneling magnetoresistance in Fe-oxide film

We fabricate Fe/Fe oxide granular film by DC sputtering and study the magnetic and transport properties in the insulator region. X-ray photoelectron spectroscopy and transmission electron microscopy confirm the coexistence of iron and Fe₂O₃. Accompanied with the nonlinear I-V curve and magnetic measurement, we investigate mechanism of sizable magnetoresistance in detail and found the spin in the interface has crucial contribution to the spin tunneling process.     

Annealing effect on tunneling magnetoresistance in MgO-based magnetic tunnel junctions with FeMn exchange-bias layer

MgO-based magnetic tunnel junctions were fabricated, with a thin pinned CoFeB layer in the unbalanced synthetic antiferromagnet part of the stack FeMn/CoFe/Ru/CoFeB. Inverted and normal tunneling magnetoresistance (TMR) values occur at low and high annealing temperatures (T_a), respectively. The TMR ratio remains inverted up to T_a=300 °C and it becomes normal around T_a=350 °C. The exchange bias of FeMn disappears at high T_a. The sign reversal of the TMR ratio is mainly attributed to the disappearance of the exchange bias due to manganese diffusion during the annealing process.