基于有限元方法的有机场效应晶体管特性模拟与实验验证

采用有限元方法,借助多物理场软件COMSOL模拟了底栅顶接触结构有机场效应晶体管电位和载流子浓度随源漏电压Vds的变化。模拟结果表明,当固定栅压V_g=-10 V时,改变V_(ds)从0~-10 V,对于电位分布,从栅极到源漏电极竖直方向有渐进的变化,而从源极到漏极的水平方向呈现由大到小明显的梯度变化。对于载流子浓度,观察到沟道处从源极向漏极逐渐减少,在靠近漏极的区域减少得尤为明显,而当源漏电压等于栅极电压时,产生夹断现象。进一步将模拟结果与实际制备的器件性能进行了对比,模拟结果与实验数据所显示的分布趋势大体相同,印证了模拟的合理性。由此表明,采用模拟方法分析有机场效应晶体管的器件特性,对于实际制备器件具有重要的指导意义。     

Lateral scaling in carbon-nanotube field-effect transistors

We have fabricated carbon-nanotube (CN) field-effect transistors with multiple, individually addressable gate segments. The devices exhibit markedly different transistor characteristics when switched using gate segments controlling the device interior versus those near the source and drain. We ascribe this difference to a change from Schottky-barrier modulation at the contacts to bulk switching. We also find that the current through the bulk portion is independent of gate length for any gate voltage, offering direct evidence for ballistic transport in semiconducting carbon nanotubes over at least a few hundred nanometers, even for relatively small carrier velocities.     

An AlGaN/GaN HEMT with enhanced breakdown and near-zero breakdown voltage temperature coefficient

An AlGaN/GaN high-electron mobility transistor (HEMT) with a novel source-connected air-bridge field plate (AFP) is experimentally verified. The device features a metal field plate that jumps from the source over the gate region and lands between the gate and drain. When compared to a similar size HEMT device with conventional field plate (CFP) structure, the AFP not only minimizes the parasitic gate to source capacitance, but also exhibits higher OFF-state breakdown voltage and one order of magnitude lower drain leakage current. In a device with a gate to drain distance of 6 μm and a gate length of 0.8 μm, three times higher forward blocking voltage of 375 V was obtained at V_GS=-5 V. In contrast, a similar sized HEMT with CFP can only achieve a breakdown voltage no higher than 125 V using this process, regardless of device dimensions. Moreover, a temperature coefficient of 0 V/K for the breakdown voltage is observed. However, devices without field plate (no FP) and with optimized conventional field plate (CFP) exhibit breakdown voltage temperature coefficients of -0.113 V/K and -0.065 V/K, respectively.     

The role of metal contacts in the stability of n-type organic field effect transistors

We are presenting a long-time bias stress stability of C₆₀-based n-type organic field effect transistors (OFETs), in bottom gate, top contacts configuration, with aluminium (Al), silver (Ag) and gold (Au) source–drain contacts. The results clearly shows that the bias stress effects in C₆₀-based n-type OFETs is similar to p-type OFETs and it can be reduced by using an appropriate metal for the source–drain contacts. During the bias stress time, the threshold voltage shift and an increase in the contacts resistance have also been measured. On the basis of the stability of the device parameters, it is proposed that the Al source–drain contact-based devices gives better stability as compared to the devices with Ag and Au source–drain contacts. Our results show that the bias stress-induced threshold voltage shift is due to the trapping of charges in the channel region and in the vicinity of the source–drain contacts.     

Physics of ultrathin-body silicon-on-insulator Schottky-barrier field-effect transistors

In this article we give an overview over the physical mechanisms involved in the electronic transport in ultrathin-body SOI Schottky-barrier MOSFETs. A strong impact of the SOI and gate oxide thickness on the transistor characteristics is found and explained using experimental as well as simulated data. We elaborate on the influence of scattering in the channel and show that for a significant barrier the on-state current is insensitive to scattering once the mean free path for scattering is larger than a characteristic length scale. In addition, recent efforts to lower the Schottky barrier at the source/drain channel interfaces are presented. Using dopant segregation during silicidation significantly lower effective Schottky barriers can be realized that allow for high performance SB-MOSFET devices. PACS 85.30.Tv; 85.35.-p; 73.30.+y     

Novel attributes of AlGaN/AlN/GaN/SiC HEMTs with the multiple indented channel

In this paper, a high performance AlGaN/AlN/GaN/SiC High Electron Mobility Transistor (HEMT) with the multiple indented channel (MIC-HEMT) is proposed. The main focus of the proposed structure is based on reduction of the space around the gate, stop of the spread of the depletion region around the source–drain, and decrement of the thickness of the channel between the gate and drain. Therefore, the breakdown voltage increases, meanwhile the elimination of the gate depletion layer extension to source/drain decreases the gate–source and gate–drain capacitances. The optimized results reveal that the breakdown voltage and the drain saturation current increase about 178% and 46% compared with a conventional HEMT (C-HEMT), respectively. Therefore, the maximum output power density is improved by factor 4.1 in comparison with conventional one. Also, the cut-off frequency of 25.2 GHz and the maximum oscillation frequency of 92.1 GHz for the MIC-HEMT are obtained compared to 13 GHz and 43 GHz for that of the C-HEMT and the minimum figure noise decreased consequently of reducing the gate–drain and gate–source capacitances by about 42% and 40%, respectively. The proposed MIC-HEMT shows a maximum stable gain (MSG) exceeding 24.1 dB at 3.1 GHz which the greatest gain is yet reported for HEMTs, showing the potential of this device for high power RF applications.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Mechanism of NBTI Recovery under Negative Voltage Stress

Recovery phenomenon is observed under negative gate voltage stress which is smaller than the previous degradation stress. We focus on the drain current to study the degradation and recovery of negative bias temperature instability (NBTI) with a real-time method. By this method, different recovery phenomena among different size devices are observed. Under negative recovery stress, the drain current gradually recovers for the large size devices and gets into recovery saturation when long recovery time is involved. For small-size devices, a step-like recovery of drain current is observed. The recovery of the drain current is mainly caused by the holes detrapping and tunnelling back to the channel surface which are trapped in oxide. The model of hole detrapping explains the recovery under negative voltage stress reasonably.     

Nanoscale SOI MOSFETs with electrically induced source/drain extension: Novel attributes and design considerations for suppressed short-channel effects

Design considerations for a below 100 nm channel length SOI MOSFET with electrically induced shallow source/drain junctions are presented. Our simulation results demonstrate that the application of induced source/drain extensions to the SOI MOSFET will successfully control the SCEs and improve the breakdown voltage even for channel lengths less than 50 nm. We conclude that if the side gate length equals the main gate length, the hot electron effect diminishes optimally.     

基于NPB的垂直构型有机发光晶体管的光电特性研究

通过将有机空穴阻挡材料BCP薄层插入垂直构型有机发光晶体管器件ITO/NPB（40nm）/Al（30nm）/NPB（20nm）/Alq₃（55nm）/Al中的不同位置对器件光电特性的影响来研究器件漏电流较大的原因以及器件中具体的载流子过程.充分证明了栅极注入的空穴对沟道中的电流有贡献.进而通过用LiF薄层修饰漏极来增强电子的注入并减小漏电流,得到了相对稳定的发光晶体管器件,其发光强度有很大提高并可很好地由栅极电压来进行调控.更换发光材料层容易得到不同颜色的发光晶体管. 关键词： 垂直构型有机发光晶体管（VOLET） 静电感应晶体管（SIT） N')" href="#">NPB （N N′-diphenyl-N')" href="#">N′-diphenyl-N N′-bis（1-naphtyl）-1')" href="#">N′-bis（1-naphtyl）-1 1′-biphenyl-4     

Ultra‐high long‐term stability of oxide‐TTFTs under current stress

In this letter the stability of transparent thin‐film transistors (TTFTs) based on the ZnO–SnO₂ (ZTO) material system is investigated. Bottom‐gate devices have been subject to electrical stress via a gate–source bias of 10 V and a drain‐source bias of 10 V leading to a drain–source current of 188 µA. In optimized TTFTs with a composition of [Zn]:[Sn] = 36:64 the relative change of the saturated field effect mobility was less than 1% and the threshold voltage shift was about 320 mV after 1000 hours of operation. This extraordinary stability of ZTO TTFTs underlines their suitability as drivers in active matrix OLED displays. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Fluorine-plasma treated AlGaN/GaN high electronic mobility transistors under off-state overdrive stress

Influences of off-state overdrive stress on the fluorine-plasma treated AlGaN/GaN high-electronic mobility transistors (HEMTs) are experimentally investigated. It is observed that the reverse leakage current between the gate and source decreases after the off-state stress, whereas the current between the gate and drain increases. By analyzing those changes of the reverse currents based on the Frenkel-Poole model, we realize that the ionization of fluorine ions occurs during the off-state stress. Furthermore, threshold voltage degradation is also observed after the off-state stress, but the degradations of AlGaN/GaN HEMTs treated with different F-plasma RF powers are different. By comparing the differences between those devices, we find that the F-ions incorporated in the GaN buffer layer play an important role in averting degradation. Lastly, suggestions to obtain a more stable fluorine-plasma treated AlGaN/GaN HEMT are put forwarded.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

双电层氧化锌薄膜晶体管偏压应力稳定性

以环保可降解的天然生物材料制备功能器件越来越受到关注,利用天然鸡蛋清作为栅介质层,采用射频磁控溅射法在其上沉积ZnO薄膜有源层,制备低压双电层氧化锌基薄膜晶体管（ZnO-TFT）并对其电学特性进行了表征,研究了器件在栅偏压和漏偏压应力下电性能的稳定性及其内在的物理机制。该ZnO-TFT器件呈现出良好的电特性,载流子饱和迁移率为5.99 cm²/（V·s）,阈值电压为2.18 V,亚阈值摆幅为0.57 V/dec,开关电流比为1.2×10⁵,工作电压低至3 V。研究表明,在偏压应力作用下,该ZnO-TFT器件电性能存在一定的不稳定性,我们认为栅偏压应力引起的电性能变化可能来源于栅介质附近及界面处的正电荷聚集、充放电效应和新陷阱态的复合效应;漏偏压应力引起的电性能变化可能来源于焦耳热引起的氧空位及沟道中的电子陷阱。     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.     

改进型异质栅对深亚微米栅长碳化硅MESFET特性影响

基于器件物理分析方法,结合高场迁移率、肖特基栅势垒降低、势垒隧穿等物理模型, 分析了改进型异质栅结构对深亚微米栅长碳化硅肖特基栅场效应晶体管沟道电势、 夹断电压以及栅下电场分布的影响.通过与传统栅结构器件特性的对比表明, 异质栅结构在碳化硅肖特基栅场效应晶体管的沟道电势中引入了多阶梯分布,加强了近源端电场; 另一方面,相比于双栅器件,改进型异质栅器件沟道最大电势的位置远离源端, 因此载流子在沟道中加速更快,在一定程度上屏蔽了漏压引起的电势变化,更好抑制了短沟道效应. 此外,研究了不同结构参数的异质栅对短沟道器件特性的影响,获得了优化的设计方案, 减小了器件的亚阈值倾斜因子.为发挥碳化硅器件在大功率应用中的优势,设计了非对称异质栅结构, 改善了栅电极边缘的电场分布,提高了小栅长器件的耐压.     

非晶铟锌氧化物薄膜晶体管的低频噪声特性与分析

本文针对底栅结构非晶铟锌氧化物薄膜晶体管的低频噪声特性开展实验与理论研究.由实验结果可知:受铟锌氧化物与二氧化硅界面处缺陷态俘获与释放载流子效应的影响,器件沟道电流噪声功率谱密度随频率的变化遵循1/fγ(γ≈0.75)的变化规律;此外,器件沟道电流归一化噪声功率谱密度随沟道长度与沟道宽度的增加而减小,证明器件低频噪声来源于沟道的闪烁噪声,可忽略源漏结接触及寄生电阻对器件低频噪声的影响.最后,基于载流子数涨落及迁移率涨落模型,提取γ因子与平均Hooge因子,为评价材料及器件特性奠定基础.     

Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface

Tremendous progress in information technology has been made possible by the development and optimization of metal oxide semiconductor field effect transistor (MOSFET) devices. For the last three decades, the dimensions of the devices have been scaled down and the complexity of the integrated circuits increased according to Moore’s law. Further scaling of the devices has been predicted by the international technology roadmap for semiconductors (ITRS). To meet the future technological requirements, much effort has been expended on increasing the capabilities of MOSFETs. Both new materials and new designs have been introduced to maintain device scaling. Most new designs were improvements of the normal planar design of the device, such as SOI and ultrathin body devices. In so-called FinFET structures, current flows through a thin silicon fin and is controlled by two gates in parallel on both sides of the fin. Vertical MOSFET devices represent a new category. In these structures the planar arrangement of the source gate and drain is turned through 90° so that they are positioned on top of each other and the current flow is perpendicular to the surface. By utilizing the 3rd dimension, the channel length can be adjusted by layer deposition and thus dispensing with advanced (and expensive) lithography. Furthermore, depending on the application, the vertical designs require less space than planar ones so that it is possible to increase integration density. The present paper gives a review of vertical MOSFET devices with current flow perpendicular to the surface. PACS 85.30     

AlGaN表面坑状缺陷及GaN缓冲层位错缺陷对AlGaN/GaN HEMT电流崩塌效应的影响

利用金属有机气相外延(MOVPE)技术生长了具有不同AlGaN表面坑状缺陷和GaN缓冲层位错缺陷密度的AlGaN/GaN 高电子迁移率晶体管(HEMT)样品,并对比研究了两种缺陷对器件栅、漏延迟电流崩塌效应的影响.栅延迟测试表明,AlGaN表面坑状缺陷会引起栅延迟电流崩塌效应和源漏电阻的增加,而且表面坑状缺陷越多,栅延迟电流崩塌程度和源漏电阻的增加越明显.漏延迟测试显示,AlGaN表面坑状缺陷对漏延迟电流崩塌影响不大,而GaN缓冲层位错缺陷主要影响漏延迟电流崩塌.研究结果表明,AlGaN表面坑状缺陷和Ga 关键词： AlGaN/GaN HEMT 电流崩塌 坑状缺陷 位错缺陷     

基于深亚微米工艺的栅接地NMOS静电放电保护器件衬底电阻模型研究

在考虑了电导率调制效应的情况下对深亚微米静电放电(electrostatic discharge, ESD)保护器件的衬底电阻流控电压源模型进行优化, 并根据轻掺杂体衬底和重掺杂外延型衬底的不同物理机制提出了可根据 版图尺寸调整的精简衬底电阻宏模型, 所建模型准确地预估了不同衬底 结构上源极扩散到衬底接触扩散间距变化对触发电压V_t1的影响. 栅接地n型金属氧化物半导体器件的击穿特性结果表明, 所提出的衬底电阻模 型与实验结果符合良好, 且仿真时间仅为器件仿真软件的7%, 为ESD保护器件版 图优化设计提供了方法支持. 关键词： 栅接地n型金属氧化物半导体器件 静电放电 衬底电阻模型