Synopsys推出新一代物理设计解决方案IC Compiler

随着工艺技术的发展，芯片复杂度不断增加，各设计目标之间的相关性和依赖性也不断提高。在设计流程中，逻辑综合、物理综合、时钟树综合．布局布线都由互相独立的工具分步完成，各步骤之间又互相影响，为了迟到设计目标，必然要在这些工具之间进行多次迭代，增加设计周期，且无法获得最佳的结果。     

新思科技将综合和布局／布线的生产效率提高2倍

新思科技有限公司近日宣布,该公司在其Galaxy设计实现平台中推出了最新的创新RTL综合工具Design Compiler2010,它将综合和物理层实现流程增速了两倍。为了满足日益复杂的设计中极具挑战性的进度要求,工程师们需要一种RTL综合解决方案,使他们尽量减少重复工作并加速物理实现进程。     

FPGA开发环境融合了物理综合技术和RTL调试工具

为调试FPGA提供图形化的物理综合流程和可视性功能 Synplify Premier为FPGA设计提供了综合环境，其物理综合流程融合了图形化物理综合技术和基于Identify RTL调试期的RTL调试工具。     

Design Compiler 2010将综合和布局布线的生产效率提高两倍

<正>全球领先的半导体设计、验证和制造的软件及知识产权(IP)供应商新思科技有限公司日前宣布:该公司在其GalaxyTM设计实现平台中推出了最新的创新RTL综合工具Design Compiler 2010,它将综合和物理层实现流程增速了两倍。为了满足日益复杂的设计中极具挑战性的进度要求,工程师们需要一种RTL综合解决方案,使他们尽量减少重复工作并加速物理实现进程。     

基于28nm数字芯片的分步式时钟树综合设计

针对常规时钟树综合得到的时钟偏移大^[1]、使用的时钟树单元多、功耗大等对芯片整体设计产生的不利因素,提出了一种分步式时钟树综合方法,即时钟树综合分两步走,第一步主要完成公共路径的时钟树综合,将时钟源转移到芯片中心处,第二步在新的时钟源即芯片中心处向四周做时钟树,由于时钟源位于芯片中心位置,这有利于平衡时钟源到叶节点的延迟。对两种时钟树综合方法进行比较,实验结果表明：分步式时钟树综合的时钟偏移比Innovus工具推荐的时钟树综合少了77ps,时钟树上使用的单元数量少了4458个,并且功耗降低了10mw左右。     

铁通机房综合布线系统路由设计及实现方法初探

针对铁通公司互联网机房现实存在的问题,研究了机房综合布线系统路由设计的适应性和合理性,应用GB50311-2007布线系统的设计原则,对后期互联网机房布线整改的实现方法作了探讨,从而达到机房布线整改的时效性,扩展性,提高机房维护效率,对公司互联网市场的发展起到更强有力的技术支持.     

一种UHF RFID标签低功耗物理设计与实现

针对超高频射频识别(UHF RFID)标签低功耗、低成本的要求,本文基于EPC Class-1 Generation-2/ISO18000-6C协议,提出一种采用多电源电压域、新型时钟树综合与局部时钟树构建的物理设计方法。该方法结合广泛应用的门控时钟技术,对芯片时钟网络进行优化设计。与传统方法相比,该方法大幅度减少时钟缓冲器插入数量,有效降低时钟网络功耗,减小芯片面积。最终验证结果表明,所设计的标签符合协议,芯片总面积为0.72mm2,其中数字逻辑面积0.15mm2,平均功耗为9.76μW,在TSMC 0.18μm的标准CMOS工艺下实现流片。     

SpringSoft发表第三代Laker定制IC设计平台与全新模拟原型工具

SpringSoft宣布现即提供LakerTM定制IC设计平台与模拟原型（AnalogPrototyping）工具。第三代热销的Laker产品系列对于模拟、混合信号、与定制数字设计与版图,提供完整的OpenAccess（OA）环境,并在28与20纳米的流程中,优化其效能与互操作性。     

FTL独辟蹊径，最新EDA综合套件瞄准非常规设计

美国FTL Systems公司正悄悄地准备一套完整的IC设计解决方案，但这家小型私有企业不打算与EDA供应商巨头针锋相对。相反，该公司表示，将集中在传统EDA工具无法解决的问题方面，特别是那些异步、需要辐射硬化或具有极大门数量的IC方面。     

基于业务平台综合网管的全业务流程监控设计思路和解决方案

通过全业务流程分析,基础支撑平台与业务的关联分析,业务量值变化分析等设计思路,提出全业务流程监控解决方案。     

Constraint transformation for IC physical design

In a top-down design methodology, design tasks are divided into simpler subtasks across levels of a hierarchy as an effective divide-and-conquer technique. For every task, tolerances are defined on all performance characteristics to take into account parasitics, mismatches, and other nondeterministic process parameter variations. Constraint transformation is a process used to translate performance specifications into subtask requirements. This paper introduces the problem of constraint transformation and describes some formal solutions for analog circuit applications. Examples illustrate the methodology and show the suitability of this approach in industrial-strength applications     

降低射频电路串扰噪声的布线方法

研究并解决了无障碍多层无网格射频电路的布线问题,主要包括三个部分:设计规则、串扰噪声限制和布线方法.首先通过设计规则计算连线参数,运用RLc模型估算串扰噪声,然后,按照需要连接的实节点个数进行归类并提出相应的布线算法.实验结果表明,该布线方法可有效地降低射频电路的串扰噪声.     

深亚微米下芯片后端物理设计方法学研究

随着摩尔定律的发展,90／65nm工艺下的大规模芯片越来越多,后端物理设计变得更加复杂,遇到了很多新问题,如高集成度、层次化设计、泄漏功耗、多角落-多模式、串扰噪声等,签收的标准也发生了变化。因此必须改进物理设计方法学,适应新的情况,来取得流片成功。     

New physical insights and models for high-voltage LDMOST IC CAD

The lateral DMOST (LDMOST), including an LDD (lightly doped drain) and the inherent BJT (bipolar junction transistor), is studied extensively using the two-dimensional device simulator PISCES. The PISCES simulations provide physical insights into the normal- and reverse-mode operations of the LDMOST, which are used for developing a comprehensive LDD LDMOST model for circuit simulation. In the modeling methodology, the LDD LDMOST is regionally partitioned into three main components (the channel, the drift region, and the BJT), and carrier-transport problems in each component are solved. The composite physical model is implemented in SPICE for HVIC (high-voltage integrated circuit) CAD and is supported by measurements. The modeling methodology is also applicable to the Resurf LDMOST     

A concurrent error detection IC in 2-μm static CMOS logic

When a comprehensive fault model is considered, static CMOS VLSI has long been prohibited from realizing concurrent error detecting (CED) circuits due to the unique analog faults (bridging and stuck-on faults). In this paper, we present the design, fabrication and testing of an experimental chip containing the integration of a totally self-checking (TSC) Berger code checker and a strongly code disjoint (SCD) built-in current sensor (BICS). This chip was fabricated by MOSIS using 2 μm p-well CMOS technology. In chip tests, all implanted faults, including analog faults, were detected as expected. We also show that the self-exercising mechanism of the SCD BICS is indeed functioning properly. This is the first demonstration of a working static CMOS CED chip     

Simulation of critical IC fabrication processes using advanced physical and numerical methods

Critical steps of IC fabrication are simulated by one- and two-dimensional computer programs using advanced physical models. Our codes deal with an arbitrary number of physical quantities such as concentrations of dopants, vacancies, interstitials and clusters, the electrostatic potential, and so on. Furthermore, they easily permit the exchange or variation of the physical models under consideration. As typical applications phenomena of coupled diffusion in one and two dimensions and dynamic arsenic clustering are investigated. The differences caused by the models of the zero space-charge approximation and the solution of the exact Poisson equation are studied by examples of As-B diffusion with various doping concentrations at different temperatures. A dynamic cluster model developed for the simulation of thermally annealed As implantations is compared to measured data of laser annealing experiments. A short outline of the mathematical and the numerical problems is given to show the amount of sophistication necessary for up-to-date process simulation.     

A structured methodology for IC photolithography synthesis insemiconductor manufacturing

A simple method for structuring the synthesis of an integrated-circuit photolithography fabrication process is described. This method has allowed Cameo, a computer-aided photolithography process synthesis system, to be built. Cameo is useful for synthesizing and evaluating a number of possible good solutions to a set of photolithography process requirements. In its current prototype implementation it is most useful for users who are familiar with integrated-circuit photolithography but are not experts. The structuring mechanism is based on dividing photolithography process design into three main subtasks corresponding to initial strategic decisions: choosing the aligner/exposer, choosing the photoresist and scheme for its application, and choosing the etch method. The synthesis work proceeds in turn at three distinct levels of detail in each subtask, the last level resulting in the complete fabrication recipe. Four types of solution methods were found to suffice for implementing nearly all steps of the synthesis: rule-based reasoning, algorithmic computation, graph interpolation, and table lookup     

Stochastic-based placement template generator for analog IC layout-aware synthesis

In this paper, a methodology for automatic generation of placement templates for analog integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit-sizing flows, is proposed. The multi-objective optimization-based placement template generator inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, i.e., placement templates. Those templates fit the current state of the optimization process and are used within the layout-aware synthesis methodology to generate the floorplan of the following candidate solutions. This innovative methodology combines the advantages of template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of the Pareto set, completely eliminating the template setup effort. Moreover, as the placement template generator runs in parallel with the layout-aware loop, it has no impact on the overall execution time. Experimental results show that the proposed methodology outperforms state-of-the-art multi-template layout-aware synthesis approaches by achieving smaller placement areas for the same performances earlier in the optimization, and further, with a strongly reduced setup effort.     

IC卡与IC卡公用电话

本文全面、系统地介绍了ＩＣ卡及ＩＣ卡公用电话的技术特点，并与磁卡及磁卡公用电话作了分析比较。