AlGaN/GaN 高电子迁移率晶体管漏电流退化机理研究

本文首先制备了与AlGaN/GaN高电子迁移率晶体管 (HEMT) 结构与特性等效的AlGaN/GaN异质结肖特基二极管, 采用步进应力测试比较了不同栅压下器件漏电流的变化情况, 然后基于电流-电压和电容-电压测试验证了退化前后漏电流的传输机理, 并使用失效分析技术光发射显微镜 (EMMI) 观测器件表面的光发射, 研究了漏电流的时间依赖退化机理. 实验结果表明: 在栅压高于某临界值后, 器件漏电流随时间开始增加, 同时伴有较大的噪声. 将极化电场引入电流与电场的依赖关系后, 器件退化前后的 log(I_FT/E)与√E 都遵循良好的线性关系, 表明漏电流均由电子Frenkel-Poole (FP) 发射主导. 退化后 log(I_FT/E)与√E 曲线斜率的减小, 以及利用EMMI在栅边缘直接观察到了与缺陷存在对应关系的“热点”, 证明了漏电流退化的机理是: 高电场在AlGaN层中诱发了新的缺陷, 而缺陷密度的增加导致了FP发射电流I_FT的增加. 关键词： AlGaN/GaN 高电子迁移率晶体管 漏电流 退化机理     

AlGaN表面坑状缺陷及GaN缓冲层位错缺陷对AlGaN/GaN HEMT电流崩塌效应的影响

利用金属有机气相外延(MOVPE)技术生长了具有不同AlGaN表面坑状缺陷和GaN缓冲层位错缺陷密度的AlGaN/GaN 高电子迁移率晶体管(HEMT)样品,并对比研究了两种缺陷对器件栅、漏延迟电流崩塌效应的影响.栅延迟测试表明,AlGaN表面坑状缺陷会引起栅延迟电流崩塌效应和源漏电阻的增加,而且表面坑状缺陷越多,栅延迟电流崩塌程度和源漏电阻的增加越明显.漏延迟测试显示,AlGaN表面坑状缺陷对漏延迟电流崩塌影响不大,而GaN缓冲层位错缺陷主要影响漏延迟电流崩塌.研究结果表明,AlGaN表面坑状缺陷和Ga 关键词： AlGaN/GaN HEMT 电流崩塌 坑状缺陷 位错缺陷     

一种基于BSIM4的屏蔽栅沟槽MOSFET紧凑型模型

提出了一种基于BSIM4的屏蔽栅沟槽MOSFET紧凑型模型.在直流模型中使用两端电势建立JFET区等效电阻模型,并引入电子扩散区等效电阻,解决了因忽视JFET区源端电势导致的电流存在误差的问题.在电容模型中,漏源电容模型在BSIM4的基础上添加了屏蔽栅-漏等效电容模型,栅漏电容模型将栅漏偏置电压修改为栅极同栅-漂移区重叠区末端节点的电势差.使用泊松方程求解该节点电势,并引入栅氧厚度因子k1、屏蔽栅氧化层厚度因子k2、等效栅-漂移区重叠长度Lovequ和等效屏蔽栅长LSHequ对栅和屏蔽栅的结构进行等效,以简化泊松方程的计算并确保该节点电势曲线的光滑性.使用Verilog-A编写模型程序,搭建实验平台测试屏蔽栅沟槽MOSFET的直流特性、电容特性和开关特性,模型仿真结果与测试数据有较好的拟合,验证了所建模型的有效性.     

非晶铟锌氧化物薄膜晶体管的低频噪声特性与分析

本文针对底栅结构非晶铟锌氧化物薄膜晶体管的低频噪声特性开展实验与理论研究.由实验结果可知:受铟锌氧化物与二氧化硅界面处缺陷态俘获与释放载流子效应的影响,器件沟道电流噪声功率谱密度随频率的变化遵循1/fγ(γ≈0.75)的变化规律;此外,器件沟道电流归一化噪声功率谱密度随沟道长度与沟道宽度的增加而减小,证明器件低频噪声来源于沟道的闪烁噪声,可忽略源漏结接触及寄生电阻对器件低频噪声的影响.最后,基于载流子数涨落及迁移率涨落模型,提取γ因子与平均Hooge因子,为评价材料及器件特性奠定基础.     

GaN MMIC中SiN介质MIM电容的可靠性

本文通过恒定应力加速实验对GaN微波单片集成电路中SiN介质MIM电容的可靠性进行了评估, 研究了高场下MIM电容的两种失效模式、临界介质击穿电荷密度以及平均失效前时间. 通过不同温度下介质电容的导电特性求解了介质内的缺陷能级.重点分析了SiN介质MIM电容的退化机理, 研究认为高应力下介质内产生新的施主型缺陷,并占据主导地位,其缺陷能级逐渐向深能级转移; 缺陷的持续增加加剧了介质内载流子的散射,导致应力后期泄漏电流降低. SiN介质MIM电容退化机理的研究为加固介质电容提供了依据.     

Al2O3绝缘层的AlGaN/GaN MOSHEMT器件研究

在研制AlGaN/GaN HEMT器件的基础上,采用ALD法制备了Al2O3 AlGaN/GaN MOSHEMT器件.通过X射线光电子能谱测试表明在AlGaN/GaN异质结材料上成功淀积了Al2O3薄膜.根据对HEMT和MOSHEMT器件肖特基电容、器件输出以及转移特性的测试进行分析发现:所制备的Al2O3,薄膜与AlGaN外延层间界面态密度较小,因而MOSHEMT器件呈现出较好的栅控性能;其次,该器件的栅压可以加至 3 V,此时的最大饱和电流达到800 mA/mm,远远高于肖特基栅HEMT器件的最大输出电流;而且栅漏反偏状态下的泄漏电流却减小了两个数量级,提高了器件的击穿电压,通过进一步分析认为泄漏电流主要来源于Fowler-Nordheim隧穿.     

AlGaN/AlN/GaN高电子迁移率器件的电容电压特性的经验拟合

利用蓝宝石衬底的AlGaN/AlN/GaN 高电子迁移率器件(HEMT)的电容电压(C-V)特性,对电子费米能级与二维电子气面密度的经验关系进行表征,其结果对器件电荷控制模型的建立,跨导及电容表达式的简化有重要意义.文章创新性地提出参数α用于表征二维势阱对沟道电子限制能力,并认为α越小则二维势阱的沟道电子限制能力越强.利用上述经验关系来拟合电容,可以获得与实测电容很好的一致性. 关键词： HEMT 费米能级 C-V特性')" href="#">C-V特性 二维势阱的电子限制能力     

透明KTN薄膜的PLD法制备及其铁电性能研究

用Sol Gel法制备KTN多晶粉末,在富氧气氛下烧结富钾KTN陶瓷,代替KTN单晶作为靶材,用PLD技术结合后期退火技术,在透明石英单晶(100)上制备出高取向的透明KTN薄膜,对薄膜厚度、折射率、伏～安(I～V)特性、介电特性进行了测试与分析.I～V特性表明,低电场强度下,I～V服从欧姆定律,高电场强度下,I～V服从平方关系,可用空间电荷限制电流模型解释.电容～测试电场频率(C～F)特性表明,低频电容色散大,高频色散小,10kHz时介电常数为12600.     

金属氧化物半导体场效应管热载流子退化的1/fγ噪声相关性研究

研究了金属氧化物半导体(MOS)器件在高、中、低三种栅压应力下的热载流子退化效应及其1/fγ噪声特性.基于Si/SiO2界面缺陷氧化层陷阱和界面陷阱的形成理论,结合MOS器件1/f噪声产生机制,并用双声子发射模型模拟了栅氧化层缺陷波函数与器件沟道自由载流子波函数及其相互作用产生能级跃迁、交换载流子的具体过程.建立了热载流子效应、材料缺陷与电参量、噪声之间的统一物理模型.还提出了用噪声参数Sfγ表征高、中、低三种栅应力下金属氧化物半导体场效应管抗热载流子损伤能力的方法.根据热载流子对噪声影响的物理机制设计了实验并验证这个模型.实验结果与模型符合良好.     

氢化非晶硅薄膜晶体管的低频噪声特性

针对氢化非晶硅薄膜晶体管(hydrogenated amorphous silicon thin film transistor,a-Si:H TFT)的低频噪声特性展开实验研究.由测量结果可知,a-Si:H TFT的低频噪声特性遵循1/f~γ(f为频率,γ≈0.92)的变化规律,主要受迁移率随机涨落效应的影响.基于与迁移率涨落相关的载流子数随机涨落模型(?N-?μ模型),在考虑源漏接触电阻、局域态俘获及释放载流子效应等情况时,对器件低频噪声特性随沟道电流的变化进行分析与拟合.基于a-Si:H TFT的亚阈区电流-电压特性提取器件表面能带弯曲量与栅源电压之间的关系,通过沟道电流噪声功率谱密度提取a-Si:H TFT有源层内局域态密度及其分布.实验结果表明:局域态在禁带内随能量呈e指数变化,两种缺陷态在导带底密度分别约为6.31×10~(18)和1.26×10~(18)cm~(-3)·eV~(-1),特征温度分别约为192和290 K,这符合非晶硅层内带尾态密度及其分布特征.最后提取器件的平均Hooge因子,为评价非晶硅材料及其稳定性提供参考.     

Photoresponse and trap characteristics of transparent AZO-gated AlGaN/GaN HEMT

AZO-gated and Ni/Au-gated AlGaN/GaN HEMTs are fabricated successfully,and an excellent transparency of AZOgated electrode is achieved.After a negative gate bias stress acts on two kinds of the devices,their photoresponse characteristics are investigated by using laser sources with different wavelengths.The effect of photoresponse on AZO-gated electrode device is more obvious than on Ni/Au-gated electrodes device.The electrons are trapped in the AlGaN barrier of AZO-gated HEMT after it has experienced negative gate bias stress,and then the electrons can be excited effectively after it has been illuminated by the light with certain wavelengths.Furthermore,the trap state density D_T and the time constantτ_T of the AZO-gated Schottky contact are extracted by fitting the measured parallel conductance in a frequency range from10 kHz to 10 MHz.The constants of the trap range from about 0.35 μs to 20.35 μs,and the trap state density increased from1.93×l0~(13)eV 1·cm~2 at an energy of 0.33 eV to 3.07×10~(11) eV~1·cm~2 at an energy of 0.40 eV.Moreover,the capacitance and conductance measurements are used to characterize the trapping effects under different illumination conditions in AZO-gated HEMTs.Reduced deep trap states' density is confirmed under the illumination of short wavelength light.     

Improved interfacial and electrical properties of GaSb metal oxide semiconductor devices passivated with acidic （NH4）2S solution

Surface passivation with acidic(NH4)2S solution is shown to be effective in improving the interfacial and electrical properties of HfO2/GaSb metal oxide semiconductor devices. Compared with control samples, the samples treated with acidic(NH4)2S solution show great improvements in gate leakage current, frequency dispersion, border trap density, and interface trap density. These improvements are attributed to the enhancing passivation of the substrates, according to analysis from the perspective of chemical mechanism, X-ray photoelectron spectroscopy, and high-resolution cross-sectional transmission electron microscopy.     

Out-of-equilibrium admittance of single electron box under strong Coulomb blockade

We study admittance and energy dissipation in an out-of-equilibrium single electron box. The system consists of a small metallic island coupled to a massive reservoir via single tunneling junction. The potential of electrons in the island is controlled by an additional gate electrode. The energy dissipation is caused by an AC gate voltage. The case of a strong Coulomb blockade is considered. We focus on the regime when electron coherence can be neglected but quantum fluctuations of charge are strong due to Coulomb interaction. We obtain the admittance under the specified conditions. It turns out that the energy dissipation rate can be expressed via charge relaxation resistance and renormalized gate capacitance even out of equilibrium. We suggest the admittance as a tool for a measurement of the bosonic distribution corresponding collective excitations in the system.     

PbS红外探测器低频噪声物理模型及缺陷表征研究

为了表征PbS薄膜光导红外探测器的材料缺陷,详细推导了1/f和产生-复合(g-r)噪声物理模型,并由实验数据验证了模型的准确性. 利用1/f噪声与表面缺陷关系,计算了不同偏压下表面陷阱密度. 得到该值随偏压升高而增加,由此得出1/f噪声与所加偏压成正比变化,与实验测试结果相一致. 在此模型基础上,研究了g-r噪声与深能级缺陷特征参量的关系,提出由低频噪声表征缺陷激活能、简并因子、俘获截面等缺陷参数的方法. 关键词： 红外探测器 1/f噪声')" href="#">1/f噪声 噪声')" href="#">g-r噪声 缺陷     

毫米波频段下MOSFET漏极电流噪声的统一模型

纳米级金属氧化物半导体场效应晶体管(MOSFET)精确的高频噪声模型是毫米波集成电路低功耗设计的重要基础,而现有的高频漏极噪声模型不仅没有融合器件的衬底效应和栅电阻效应,也没有充分考虑器件的频率和偏置依赖性。针对上述问题,基于纳米MOSFET器件的物理特性,并结合漂移扩散方程和有效栅极过载,建立统一表征强反区到弱反区的频率和偏置依赖性的漏极噪声模型,使之便于移植到先进设计系统(ADS)仿真设计。通过所建模型的仿真结果与实验测试结果进行比较,验证所建模型的准确性。同时比较所建模型对130 nm和40 nm MOSFET两种不同工艺器件的实用性,验证其对表征40 nm MOSFET的毫米波噪声特性的优越性。     

Passivation of n-GaAs (100) surface by a Langmuir-Blodgett film

We report the results of passivation of n-GaAs surface by Langmuir-Blodgett films. The capacitance-voltage and current-voltage characteristics in a metal-insulator-semiconductor configuration fabricated using films as insulators, show that the frequency dispersion of the accumulation capacitance is small, indicating that the high frequency capacitance under accumulation is due to the LB film. It has been shown that it reduces the surface barrier characteristic of GaAs surfaces, and may offer hope for unpinning the surface Fermi level. We offer a possible explanation for these findings in terms of the advanced unified defect and the effective work function models.     

Application of superlattice gate and modulation-doped buffer for GaAs power MESFET grown by MBE

A new power GaAs MESFET (SGMBT), using the undoped superlattice gate and modulation-doped (MD) buffer, has been fabricated successfully by MBE. A much higher gate-drain breakdown voltage (30 V) and lower gate reverse leakage current have been obtained due to the existence of the undoped AlGaAs/GaAs superlattice gate insulator. The use of MD buffer structure introduces a high output resistance and low trap concentration at AlGaAs/GaAs interface. The degradation region at channel-buffer interface is estimated to be smaller than 40 Å. Thus the sharpness and smoothness between active channel and buffer is truly improved by the insertion of MD structure. The maximum output saturation current and output power of SGMBT are 300 mA/mm and 0.67 W/mm, respectively. By optimizing the device geometry and gate dimension, the output performance of SGMBT can be improved further.     

Equivalent distributed capacitance model of oxide traps on frequency dispersion of C-V curve for MOS capacitors

An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C-V curve of MOS capacitors measured for a frequency range from 1 kHz to1 MHz.The proposed model is based on the Fermi-Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal.The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data.Simulations indicate thatthe capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface,with negligible effects from the traps far from the interface,and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed.In addition,by excluding the negligible effect of oxide-trap conductance,the model avoids the use of imaginary numbers and complex calculations,and thus is simple and intuitive.     

Impact of gate offset in gate recess on DC and RF performance of InAlAs/InGaAs InP-based HEMTs

A set of 100-nm gate-length InP-based high electron mobility transistors (HEMTs) were designed and fabricated with different gate offsets in gate recess. A novel technology was proposed for independent definition of gate recess and T-shaped gate by electron beam lithography. DC and RF measurement was conducted. With the gate offset varying from drain side to source side, the maximum drain current (I_ds,max) and transconductance (g_m,max) increased. In the meantime, f_T decreased while f_max increased, and the highest f_max of 1096 GHz was obtained. It can be explained by the increase of gate-source capacitance and the decrease of gate-drain capacitance and source resistance. Output conductance was also suppressed by gate offset toward source side. This provides simple and flexible device parameter selection for HEMTs of different usages.     

The physical process analysis of the capacitance-voltage characteristics of AlGaN/AlN/GaN high electron mobility transistors

This paper deduces the expression of the Schottky contact capacitance of AlGaN/AlN/GaN high electron mobility transistors (HEMTs), which will help to understand the electron depleting process. Some material parameters related with capacitance-voltage profiling are given in the expression. Detailed analysis of the forward-biased capacitance has been carried on. The gate capacitance of undoped AlGaN/AlN/GaN HEMT will fall under forward bias. If a rising profile is obviously observed, the donor-like impurity or trap is possibly introduced in the barrier.