应变硅PMOSFET中应变的LACBED研究

本文报道了应变硅p型金属氧化物半导体场效应晶体管(PMOSFET)沟道中的局部应变的大角度会聚束电子衍射表征.由于源和漏极区预非晶化锗离子注入工艺在源漏区引入了大量的缺陷,导致在截面电镜样品中存在切应变.利用大角度会聚束电子衍射(LACBED)测量了沟道区的压应变和切应变,并讨论了沟道区产生巨大压应变(2%以上)的原因.     

应变硅pMOS晶体管沟道应变的有限元研究

通过有限元方法,研究了一种采用SiGe源漏结构的pMOS晶体管中硅沟道的应变及其分布情况,模拟计算结果与利用会聚束电子衍射方法测量得到的数据能够较好地吻合,验证了模拟模型及方法的正确性。结果表明:提高源漏SiGe中的Ge组分、减小源漏间距、增加源漏的刻蚀深度和抬高高度,能有效增加沟道的应变量,为通过控制应变改善载流子迁移率提供了设计依据。     

纳米MOSFET的多栅结构和应变硅纳米线结构

介绍了在进入22 nm技术节点后MOSFET器件的两个发展方向,即多栅结构和应变硅纳米线结构.首先通过分析特征长度与有效栅极数量的关系,表明多栅结构器件可以有效增强栅极对沟道的控制,抑制短沟道效应,接近理想的亚阈值斜率;然后分析了应变对能带结构的影响,从理论上论述了应变沟道可以显著提高载流子迁移率;最后介绍了悬浮硅纳米...     

Pt／Si外延膜界面处Si基体中应力场的LACBED研究

我们利用大角度会聚束电子衍射(简称LACBED)的方法对Pt/Si外延膜界面处Si基体中的应力场进行了研究。Pt/Si外延膜试样是用蒸镀的方法在基体Si片上沿(111)面外延生成金属Pt而成。X-射线分析结果表明Pt沿Si(111)面外延生长很好。图1是Pt/Si界面的明场象。左面为衬底Si,右边为外延生长Pt层。图2是电子束照射在界面附近不同地方的LACBED花样。图中界面在LACBED花样中所处的位置可以清晰地看出。图2(a)可以看出,当界面远离     

应变硅NMOS晶体管沟道应变的模拟研究

建立了一种基于硅/锗硅异质结构的应变硅NMOS晶体管的有限元模型,通过模拟研究了沟道区的应变分布及其与器件参数的关系。结果表明,提高锗硅虚拟衬底中锗的摩尔组分、减小应变硅层厚度,可以增加沟道应变。此外,应变量还随器件结构长度的增加而增加。研究结果可为应变硅器件的设计、工艺优化提供参考依据。     

纳米级应变硅MOSFET的有限元与TCAD模拟研究

基于有限元方法对一款具有SiGe源/漏结构的纳米PMOSEFT进行了建模与分析,沟道应变的计算结果与CBED实验测量值呈现良好的一致性,最小误差仅为1.02×10-4.对新型的SiC源/漏结构的纳米NMOSFET的类似研究表明,栅长越短,应变对沟道的影响越显著.另一方面,采用TCAD工具Sentaurus通过工艺级仿真...     

低温制备应变硅沟道MOSFET栅介质研究

分别对300 °C下采用等离子体增强化学气相淀积(PECVD)和700 °C下采用热氧化技术制备应变硅沟道MOS器件栅介质薄膜进行了研究.采用PECVD制备SiO2栅介质技术研制的应变硅沟道PMOSFET(W/L＝20 μm/2 μm)跨导可达45 mS/mm(300 K), 阈值电压为1.2 V;在700 °C下采用干湿氧结合,制得电学性能良好的栅介质薄膜,并应用于应变硅沟道PMOSFET(W/L＝52 μm/4.5 μm)器件研制,其跨导达到20mS/mm(300 K),阈值电压为0.4 V.     

一种新颖的应变Si沟道 pMOSFET制作技术

在应变Si沟道异质结场效应晶体管(HFET)制作过程中,引入分子束外延(MBE)低温Si(LT-Si)技术,大大减少了弛豫SiGe层所需的厚度.TEM结果表明,应变Si层线位错密度低于106cm-2.原子力显微镜(AFM)测试表明,其表面均方粗糙度小于1.02nm.器件测试结果表明,与相同条件下的体Si pMOSFET相比,空穴迁移率提高了25%.     

一种新颖的应变Si沟道pMOSFET制作技术

在应变Si沟道异质结场效应晶体管（HFET）制作过程中，引入分子束外延（MBE）低温Si (LT-Si）技术，大大减少了弛豫SiGe层所需的厚度. TEM结果表明，应变Si层线位错密度低于1E6cm-2.原子力显微镜（AFM）测试表明，其表面均方粗糙度小于1.02nm.器件测试结果表明，与相同条件下的体Si pMOSFET相比，空穴迁移率提高了25%.     

一种新颖的应变Si沟道 pMOSFET制作技术

在应变Si沟道异质结场效应晶体管(HFET)制作过程中,引入分子束外延(MBE)低温Si(LT-Si)技术,大大减少了弛豫SiGe层所需的厚度.TEM结果表明,应变Si层线位错密度低于106cm-2.原子力显微镜(AFM)测试表明,其表面均方粗糙度小于1.02nm.器件测试结果表明,与相同条件下的体Si pMOSFET相比,空穴迁移率提高了25%.     

Nanoscale strained-Si MOSFET physics and modeling approaches: a review

An attempt has been made to give a detailed review of strained silicon technology. Various device models have been studied that consider the effect of strain on the devices, and comparisons have been drawn. A review of some modeling issues in strained silicon technology has also been outlined. The review indicates that this technology is very much required in nanoscale MOSFETs due to its several potential benefits, and there is a strong need for an analytical model which describes the complete physics of the strain technology.     

Nanoscale strained-Si MOSFET physics and modeling approaches: a review

In this paper, an attempt has been made to give a detailed review of strained silicon technology. Various device models have been studied in this paper that consider the effect of strain on the devices and their comparisons have been drawn. A review of some modeling issues in strained silicon technology has also been outlined. The review indicates that this technology is very much required in nanoscale MOSFETs due to its several potential benefits and there is a strong need of an analytical model which describes the complete physics of the strain technology.     

非对称异质双栅应变硅MOSFETs 二维模型研究

基于对二维泊松方程的精确求解,本文对全耗尽型非对称异质双栅应变硅MOSFET的二维表面势,表面电场,阈值电压进行了研究。模型结果和二维数值模拟器的结果很吻合。此外并对该器件的物理作了深入的研究。该模型对设计全耗尽型非对称异质双栅应变硅MOSFET器件有着重要的指导作用.     

A two-dimensional analytical model of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs

On the basis of the exact resultant solution of two dimensional Poisson’s equations,a new accurate two-dimensional analytical model comprising surface channel potentials,a surface channel electric field and a threshold voltage for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is successfully developed. The model shows its validity by good agreement with the simulated results from a two-dimensional numerical simulator.Besides offering a physical insight into device physics,the model provides basic design guidance for fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.     

沟槽型MOSFET的发展

在功率变换器中沟槽型MOSFET取代功率二极管传递能量有两个优点：可以用PWM驱动电路灵活地控制MOSFET为不同的负载提供所需的能量;导通电阻低,能耗小。文章介绍了新研究出来的厚栅氧MOSFET,RSOMOSFET,集成肖特基二极管的沟槽型MOSFET,并对它们的机理和性能进行了阐述和分析。     

关于MOSFET的双峰效应量化评估研究

介绍一种关于双峰效应(Double-Hump)的评估方法.通过对MOSFET的Id-Vg曲线的分析,双峰效应的程度可以用数字化评估.采取这种量化表征,细致地研究了双峰效应与掺杂浓度的关系.建立了MOS的Vt 和Punch-through的粒子注入有效浓度和双峰效应的相互关系模型.它们之间的相互关系与现存的理论一致.     

A novel surface potential-based short channel MOSFET model for circuit simulation

In this paper a novel analytical approximation method for surface potential (ψ_s) calculation in compact MOSFET model is presented. It achieves excellent accuracy and good calculation speed over all regions from accumulation to strong inversion. With this approximation method, a surface potential-based compact model for short channel MOSFET is developed. Comparison with measured data is also presented to validate the new model.     

First-principle study of puckered arsenene MOSFET

Two-dimensional material has been regarded as a competitive silicon-alternative with a gate length approaching sub-10 nm, due to its unique atomic thickness and outstanding electronic properties. Herein, we provide a comprehensively study on the electronic and ballistic transport properties of the puckered arsenene by the density functional theory coupled with nonequilibrium Green’s function formalism. The puckered arsenene exhibits an anisotropic characteristic, as effective mass for the electron/hole in the armchair and zigzag directions is 0.35/0.16 m₀ and 1.26/0.32 m₀. And it also holds a high electron mobility, as the highest value can reach 20 045 cm²V^–1s^–1. Moreover, the puckered arsenene FETs with a 10-nm channel length possess high on/off ratio above 10⁵ and a steep subthreshold swing below 75 mV/dec, which have the potential to design high-performance electronic devices. Interestingly, the channel length limit for arsenene FETs can reach 7-nm. Furthermore, the benchmarking of the intrinsic arsenene FETs and the 32-bit arithmetic logic unit circuits also shows that the devices possess high switching speed and low energy dissipation, which can be comparable to the CMOS technologies and other CMOS alternatives. Therefore, the puckered arsenene is an attractive channel material in next-generation electronics.     

轻掺杂漏(LDD)MOSFET的数值模拟

轻掺杂漏(LDD)MOSFET是一种已用在VLSI中的新型MOSFET结构.为了有效地进行LDD MOSFEI的优化设计,我们在二维数值模拟器MINIMOS的基础上,修改了边界条件及输入输出格式,考虑了轻掺杂区的杂质分布,研制成功了一种既适用于常规以MOSFET,又适用于LDD MOSFET的二维数值模拟程序FD-MINIMOS.应用该程序对LDD MOSFET的一系列直流特性模拟的结果表明,不同的轻掺杂浓度对于抑制沟道电场及热电子效应具有不同的效果,为轻掺杂区优化设计提供了重要信息.