CMOS circuit testability

CMOS circuits present unique testing problems. Although open faults in CMOS circuits can be statistically tested, a sequence of patterns is required to guarantee a test. In addition, connections in the circuit layout affect testability. An automatic test generator has been developed to generate test sequences which will detect open CMOS faults.     

Automated synthesis for testability

The authors present an integrated, compiler-driven approach to digital chip design that automates mask layout and test-pattern generation for 100% stuck-at fault coverage. This approach is well suited for designs where it is most important the minimize the design cycle time rather than the silicon area. The authors show that by compiling from a unified design specification followed by logic synthesis it is possible to reduce the problem of automatic test-pattern generation. They present a language-based design capture and logic synthesis with hierarchical test pattern generation and redundancy removal techniques. A section on benchmark results highlights the close coupling of a language-based design specification, logic synthesis, and testability     

Bibliography of literature on testability

This paper briefly discusses the subject of testability. A list of selected references on testability and related areas is presented.     

Defect-oriented testability for asynchronous ICs

For a CMOS manufacturing process, asynchronous ICs are similar to synchronous ICs. The defect density distributions are similar, and hence, so are the fault models and fault-detection methods. So, what makes us think that asynchronous circuits are much harder to test than synchronous circuits? Because the effectiveness of best known test methods for synchronous circuits drops when applied to asynchronous circuits? They may very well be a temporal hurdle. Many test methods have already been reevaluated and successfully adapted from the synchronous to the asynchronous test domain. The paper addresses one of the final hurdles: I_DDQ testing. This type of test method, based on measuring the quiescent power supply current, is very effective for detecting (resistive) bridging faults in CMOS circuits. Detection of bridging faults is crucial, because they model the majority of today's manufacturing defects. I_DDQ fault effects are sensitized in a particular state or set of states and can only be detected if we stop the circuit operation right there. This is a problem for asynchronous circuits, because their operation is self-timed. In the paper, we quantify the impact of self timing on the effectiveness of I_DDQ -based test methods for bridging faults, and propose a Design-for-Test (DfT) approach to develop a low-cost DfT solution. For comparison, we do the same for logic voltage testing and stuck-at faults. The approach is illustrated on circuits from Tangram, the asynchronous design-style employed at Philips Research, but it is applicable to asynchronous circuits in general     

Incorporating testability considerations in high-level synthesis

In this article we propose two novel methods to improve the testability of the designs produced by high-level synthesis tools. Our first method, loop-breaking algorithm, identifies self-loops in a design generated by a high-level synthesis system and eliminates as many of these loops as possible by altering the register and module bindings. The second method, BINET with test cost, is a binding algorithm that takes the cost of testing into account during the binding phase of the high-level synthesis. The test cost considered in this article is a function of the number of self-loops in the synthesized design. Thus it generates only those solutions that have fewer if any self-loops. Finally we put the two methods together in which we first use BINET with test cost to produce nearly self-loop free designs and we further improve their testability by using the loop-breaking algorithm. We applied these methods to synthesis benchmark circuits and the results of our study, given in this article, show that the designs produced by our method have indeed reduced testability overhead and improved testability.     

微处理器指南

Actel Corp (www.actel.com) Actel公司的8位Core8051微控制器内核的目标是那些依靠该公司的非易失性单片ProASIC Plus、Axcelerator、SX-A和RTSX-S FPGA工作的消费、汽车、工业、军事和航天应用.该内核在一个周期内执行所有ASM51指令,并具有13个四优先级中断、32个I/O端口、2个定时器、1个可编程串口.您可以把Core8051与其它ActelIP内核结合起来,增强它的功能.     

Microprocessor interfaces

The letter shows that the use of frontend logic allows microprocessor interfaces to be designed systematically and simply, using logic-free channels. Their impletnentation requires no monostables, local clocks or any other form of timing signals.     

Energy minimization and design for testability

The problem of fault detection in general combinational circuits is NP-complete. The only previous result on identifying easily testable circuits is due to Fujiwara who gave a polynomial time algorithm for detecting any single stuck fault inK-bounded circuits. Such circuits may only contain logic blocks with no more thanK input lines and the blocks are so connected that there is no reconvergent fanout among them. We introduce a new class of combinational circuits called the (k, K)-circuits and present a polynomial time algorithm to detect any single or multiple stuck fault in such circuits. We represent the circuit as an undirected graphG with a vertex for each gate and an edge between a pair of vertices whenever the corresponding gates have a connection. For a (k, K)-circuit,G is a subgraph of ak-tree, which, by definition, cannot have a clique of size greater thank+1. Basically, this is a restriction on gate interconnections rather than on the function of gates comprising the circuit. The (k, K)-circuits are a generalization of Fujiwara'sK-bounded circuits. Using the bidirectional neural network model of the circuit and the energy function minimization formulation of the fault detection problem, we present a test generation algorithm for single and multiple faults in (k, K)-circuits. This polynomial time aggorithm minimizes the energy function by recursively eliminating the variables.     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off- and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

Improving the testability of switched-capacitor filters

A design-for-test methodology for SC filters is presented, based on an architecture using some additional circuitry and providing extra capabilities for both off-and on-line tests. The approach uses a comparison (voting) mechanism to indicate whether or not two copies of a filter element (a biquad, for instance) have a similar response during their actual operation. The design and implementation of a few filter examples are included to assess the potential usefulness of this new approach.     

Integrating testability with design space exploration

Built-in self-test (BIST) has emerged as a promising test solution for high-speed, deep sub-micron VLSI circuits. Traditionally, the testability insertion phase comes after functional logic synthesis and verification in the design cycle. This creates two separate optimisation processes: functional optimisation followed by BIST insertion and optimisation. The first deals with functional design behaviour, while the second deals with test behaviour. Considering testability at such a late stage in the design flow limits efficient design space exploration. In this paper, we consider testability as a design objective alongside area and delay. We extend the concept of design space to include testability and show how this enhanced design space can be used by a high-level synthesis tool. We demonstrate that by taking testability into account at an early stage, we can generate better designs than by leaving BIST insertion to the end of the design cycle.     

微处理器与DSP

多核远程通信处理器；带有片上闪存的高性能16位MCU；集成CAN网络的32位微控制器；采用90nm工艺带片上闪存的微控制器；用于AMD皓龙四核处理器的多核处理器开发工具；     

Microprocessor prototyping kits

The microprocessor market is expanding at an amazing rate. The only element of this market more surprising than its rate of growth is its escalating number of new vendors. The time has already arrived when you cannot tell the players without a score card. The score cards in the microprocessor world consist of chip sets, memory, I/O controls, specifications, schematics, support devices, and available software for the various microprocessors. These score cards are the prototyping kits that are so popular today.     

Microprocessor pin predicting

We verified that contemporary microprocessors follow a form of Rent's rule as applicable for functionally partitioned circuits and, hence, present far fewer pins than that predicted by the SIA. We have also suggested a correction scheme for application of Rent's rule to recent VLSI circuits that would yield the correct (slower) rate of increase in pin requirements of these circuits. Finally, the reasons for using such a large number of power and ground pins in current VLSI circuits have been elaborated in detail     

微处理器与DSP

低功耗高性能微控制器赛恩科技推出最新的低功耗、高性能eCOG1X微控制器产品家族eCOG1X。     

Microprocessor technology trends

The rapid pace of advancement of microprocessor technology has shown no sign of diminishing, and this pace is expected to continue in the future. Recent trends in such areas as silicon technology, processor architecture and implementation, system organization, buses, higher levels of integration, self-testing, caches, coprocessors, and fault tolerance are discussed, and expectations for further advances are highlighted. How these trends and expectations will drive the markets and applications, and vice versa, is also explored.