High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Organic thin‐film transistor fabricated between flexible films by thermal lamination

We propose a novel and complementary method for fabrication of flexible electronics. This method is not based on conventional printing using inks, but is based on the application of a toner‐based method such as Xerox or laser printing, followed by a lamination process. The lamination method is a solvent‐free and material‐saving process that simultaneously seals the devices, and the fabricated flexible devices have structural durability against bending. We have also shown that thermal lamination has an oriented growth effect, and the electrical characteristics of flexible organic field‐effect transistors did not degrade under a bending radius of 1 mm.

     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Influence of polymer dielectric surface energy on thin‐film transistor performance of solution‐processed triethylsilylethynyl anthradithiophene (TES‐ADT)

This study investigates the correlation between surface energy of polymer dielectrics and the film morphology, microstructure, and thin‐film transistor performance of solution‐processed 5,11‐bis(triethylsilylethynyl) anthradithiophene (TES‐ADT) films. The low surface energy polyimide (PI) dielectric induced large grains with strong X‐ray reflections for spin‐cast TES‐ADT films in comparison to high surface en‐ ergy poly(4‐vinyl phenol) (PVP) dielectric. Furthermore, thin‐film transistors based on spin‐cast TES‐ADT films on PI dielectric exhibited enhanced electrical performance, small hysteresis, and high stability under bias stress with carrier mobility as high as 0.43 cm²/Vs and a current on/off ratio of 10⁷. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Investigation of AlGaN/GaN fluorine plasma treatment enhancement-mode high electronic mobility transistors by frequency-dependent capacitance and conductance analysis

This paper reports fluorine plasma treatment enhancement-mode HEMTs (high electronic mobility transistors) EHEMTs and conventional depletion-mode HEMTs DHEMTs fabricated on one wafer using separate litho-photography technology. It finds that fluorine plasma etches the AlGaN at a slow rate by capacitance--voltage measurement. Using capacitance--frequency measurement, it finds one type of trap in conventional DHEMTs with τ_T=(0.5-6) ms and D_T= (1 - 5) × 10¹³ cm^-2·eV^-1. Two types of trap are found in fluorine plasma treatment EHEMTs, fast with τ_T(f)=(0.2-2) μs and slow with τ_T(s)=(0.5-6) ms. The density of trap states evaluated on the EHEMTs is D_T(f)=(1 - 3) × 10¹² cm^-2·eV^-1 and D_T(s)=(2 - 6) × 10¹² cm^-2·eV^-1 for the fast and slow traps, respectively. The result shows that the fluorine plasma treatment reduces the slow trap density by about one order, but introduces a new type of fast trap. The slow trap is suggested to be a surface trap, related to the gate leakage current.     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Fabrication of 6,13‐bis(triisopropyl‐silylethynyl)–pentacene thin‐film transistors with the silver ink transfer method using a polymer stamp

We fabricated 6,13‐bis(triisopropylsilylethynyl)–pentacene (TIPS–pentacene) thin film transistors using a direct metal transfer method. Using different metals, such as Au and Ag ink, electrode patterns are formed from the relief region of the polymer mold. TIPS–pentacene TFTs using the Ag ink transfer method show a similar performance to those using the Au metal transfer method. This method has advantages over the Au metal transfer method because it does not require vacuum equipment and a dry etching process. The self‐assembled monolayer (SAM) treated device exhibits a carrier mobility of 9.5 × 10^–2 cm²/V · s, and an on/off ratio of 4.6 × 10⁴. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Electrical in‐situ characterisation of interface stabilised organic thin‐film transistors

We report on the electrical in‐situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom‐gate/bottom‐contact (coplanar) configuration are electrically characterised in‐situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO₂ with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor param‐ eters is studied on a bi‐layer dielectric of a 150 nm of SiO₂ and 20 nm of poly((±)endo,exo‐bicyclo[2.2.1]hept‐5‐ene‐2,3‐dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO₂ dielectric. The thin layer of PNDPE, which is an intrinsically photo‐patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Highly stable amorphous indium‐zinc‐oxide thin‐film transistors with back‐channel wet‐etch process

The stabilities of amorphous indium‐zinc‐oxide (IZO) thin film transistors (TFTs) with back‐channel‐etch (BCE) structure are investigated. A molybdenum (Mo) source/drain electrode was deposited on an IZO layer and patterned by hydrogen peroxide (H₂O₂)‐based etchants. Then, after etching the Mo layer, SF₆ plasma with direct plasma mode was employed and optimized to improve the bias stress stability. Scanning electron microscopy and X‐ray photoelectron spectroscopic analysis revealed that the etching residues were removed efficiently by the plasma treatment. The modified BCE‐ TFTs showed only threshold voltage shifts of 0.25 V and –0.20 V under positive/negative bias thermal stress (P/NBTS, V_GS = ±30 V, V_DS = 0 V and T = 60 °C) after 12 hours, respectively. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Effect of antimony doping on the low‐temperature performance of solution‐processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution‐processed indium oxide (InO_x) thin film transistors (TFTs) were examined. The Sb‐doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high I_ON/OFF ratio of 4.6 cm²/V s, 0.29 V/decade, 1.9 V, and 3 × 10⁷, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InO_x TFTs. This improvement was attributed to the reduction of oxygen‐related defects and/or the existence of the lone‐pair s‐electron of Sb³⁺ in amorphous InSbO films. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Performance improvement in pentacene organic thin film transistors by inserting a C60 ultrathin layer

The contact effect on the performances of organic thin film transistors is studied here. A C₆₀ ultrathin layer is inserted between Al source--drain electrode and pentacene to reduce the contact resistance. By a 3 nm C₆₀ modification, the injection barrier is lowered and the contact resistance is reduced. Thus, the field-effect mobility increases from 0.12 to 0.52 cm²/(V·s). It means that inserting a C₆₀ ultra thin layer is a good method to improve the organic thin film transistor (OTFT) performance. The output curve is simulated by using a charge drift model. Considering the contact effect, the field effect mobility is improved to 1.15 cm²/(V·s). It indicates that further reducing the contact resistance of OTFTs should be carried out.     

A high mobility C60 field-effect transistor with an ultrathin pentacene passivation layer and bathophenanthroline/metal bilayer electrodes

C₆₀ field-effect transistor (OFET) with a mobility as high as 5.17 cm²/V·s is fabricated. In our experiment, an ultrathin pentacene passivation layer on poly-(methyl methacrylate) (PMMA) insulator and a bathophenanthroline (Bphen)/Ag bilayer electrode are prepared. The OFET shows a significant enhancement of electron mobility compared with the corresponding device with a single PMMA insultor and an Ag electrode. By analysing the C₆₀ film with atomic force microscopy and X-ray diffraction techniques, it is shown that the pentacene passivation layer can contribute to C₆₀ film growth with the large grain size and significantly improve crystallinity. Moreover, the Bphen buffer layer can reduce the electron contact barrier from Ag electrodes to C₆₀ film efficiently.     

Mobility Enhancement of P3HT‐Based OTFTs upon Blending with Au Nanorods

The mobility enhancement of organic thin‐film transistors based on poly(3‐hexylthiophene) (P3HT) by incorporating gold nanorods (Au NRs) is reported. Through varying the doping concentration and surface modifier of the Au NRs in P3HT matrix, the P3HT/Au composite with 0.5 mg mL^?1 pyridine‐capped Au NRs exhibits a hole mobility of 0.059 cm² V^?1 s^?1, this value is seven times higher than that of pristine P3HT. This remarkable improvement of mobility originates from the enhanced crystallinity and optimized orientation of P3HT after doping with Au NRs. In addition, the appropriate surface modification can produce more‐efficient hole conduction of Au NRs.     

The Organosilicon thin Film Deposited Using an Atmospheric Pressure Dual‐Frequency 50 kHz/33 MHz Frequency MicroPlasma Jet

In this paper, an atmospheric pressure dual‐frequency (50 kHz/33 MHz) micro‐plasma jet was used to deposit organosilicon film. The discharge generated in atmospheric environment. Plasma composition was characterized by optical emission spectroscopy. With introduction of tetraethyl orthosilicate, we observed various spectra, for example Si(251.6 nm), OH(308.9 nm), C(247.8 nm), O(777.5 nm). Abundant reactive radical species which are benefit to film deposition were generated in plasma. The deposited film was characterized by scanning electron microscopy, X‐ray photoelectron spectroscopy and Fourier transform infrared spectroscopy. The film is mostly composed of Si and O. The film has Si‐O‐Si backbone with a small number of organic component (‐CHx). (© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Enhancement-mode AlGaN/GaN high electronic mobility transistors with thin barrier

An enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMTs) was fabricated with 15-nm AlGaN barrier layer. E-mode operation was achieved by using fluorine plasma treatment and post-gate rapid thermal annealing. The thin barrier depletion-HEMTs with a threshold voltage typically around --1.7 V, which is higher than that of the 22-nm barrier depletion-mode HEMTs (--3.5 V). Therefore, the thin barrier is emerging as an excellent candidate to realize the enhancement-mode operation. With 0.6-μ m gate length, the devices treated by fluorine plasma for 150-W RF power at 150 s exhibited a threshold voltage of 1.3 V. The maximum drain current and maximum transconductance are 300 mA/mm, and 177 mS/mm, respectively. Compared with the 22-nm barrier E-mode devices, V_T of the thin barrier HEMTs is much more stable under the gate step-stress.