High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

One decade of fully transparent oxide thin‐film transistors: fabrication,performance and stability

We review the history of fully transparent oxide thin‐film transistors. Their performance and stability increased during the past ten years of their existence, thus enabling the design of novel applications in transparent electronics. However, certain disadvantages of the well established leading technology of metal–insulator–semiconductor field‐effect transistors (MISFETs), adapted from the silicon‐based complementary metal–oxide–semiconductor (CMOS) and thin‐film transistor technology, may be overcome by alternative transistor designs like metal–semiconductor field‐effect transistors (MESFETs). We compare the stability of published transparent MISFET with our transparent MESFET (TMESFET) technology against bias stress, towards illumination, at elevated temperatures and long‐term stability.

     

Effect of antimony doping on the low‐temperature performance of solution‐processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution‐processed indium oxide (InO_x) thin film transistors (TFTs) were examined. The Sb‐doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high I_ON/OFF ratio of 4.6 cm²/V s, 0.29 V/decade, 1.9 V, and 3 × 10⁷, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InO_x TFTs. This improvement was attributed to the reduction of oxygen‐related defects and/or the existence of the lone‐pair s‐electron of Sb³⁺ in amorphous InSbO films. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Electrical in‐situ characterisation of interface stabilised organic thin‐film transistors

We report on the electrical in‐situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom‐gate/bottom‐contact (coplanar) configuration are electrically characterised in‐situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO₂ with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor param‐ eters is studied on a bi‐layer dielectric of a 150 nm of SiO₂ and 20 nm of poly((±)endo,exo‐bicyclo[2.2.1]hept‐5‐ene‐2,3‐dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO₂ dielectric. The thin layer of PNDPE, which is an intrinsically photo‐patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

非晶铟锌氧化物薄膜晶体管的低频噪声特性与分析

本文针对底栅结构非晶铟锌氧化物薄膜晶体管的低频噪声特性开展实验与理论研究.由实验结果可知:受铟锌氧化物与二氧化硅界面处缺陷态俘获与释放载流子效应的影响,器件沟道电流噪声功率谱密度随频率的变化遵循1/fγ(γ≈0.75)的变化规律;此外,器件沟道电流归一化噪声功率谱密度随沟道长度与沟道宽度的增加而减小,证明器件低频噪声来源于沟道的闪烁噪声,可忽略源漏结接触及寄生电阻对器件低频噪声的影响.最后,基于载流子数涨落及迁移率涨落模型,提取γ因子与平均Hooge因子,为评价材料及器件特性奠定基础.     

高迁移率非晶铟镓锌氧化物薄膜晶体管的制备与特性研究

由于铟镓锌氧化物(IGZO) 薄膜具有高迁移率和高透过率的特点, 它作为有源层被广泛的应用于薄膜晶体管(TFT). 本文利用磁控溅射方法制备了TFT的有源层IGZO和源漏电极, 用简单低成本的掩膜法控制沟道的尺寸, 制备了具有高迁移率、底栅结构的n型非晶铟镓锌氧化物薄膜晶体管 (IGZO-TFT). 利用X 射线衍射仪(XRD) 和紫外可见光分光光度计分别测试了IGZO薄膜的衍射图谱和透过率图谱, 研究了IGZO薄膜的结构和光学特性. 通过测试IGZO-TFT的输出特性和转移特性曲线, 讨论了IGZO有源层厚度对IGZO-TFT特性的影响. 制备的IGZO-TFT器件的场效应迁移率高达15.6 cm²·V^-1·s^-1, 开关比高于10⁷. 关键词： 非晶铟镓锌氧化物 薄膜晶体管 有源层     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

P‐type tin‐oxide thin film transistors for blue‐light detection application

We reported the characteristics of p‐type tin‐oxide (SnO) thin film transistors (TFTs) upon illumination with visible light. Our p‐type TFT device using the SnO film as the active channel layer exhibits high sensitivity toward the blue‐light with a high light/dark read current ratio (I_light/I_dark) of 8.2 × 10³ at a very low driven voltage of <3 V. Since sensing of blue‐light radiation is very critical to our eyes, the proposed p‐type SnO TFTs with high sensitivity toward the blue‐light show great potential for future blue‐light detection applications.

     

Organic thin‐film transistor fabricated between flexible films by thermal lamination

We propose a novel and complementary method for fabrication of flexible electronics. This method is not based on conventional printing using inks, but is based on the application of a toner‐based method such as Xerox or laser printing, followed by a lamination process. The lamination method is a solvent‐free and material‐saving process that simultaneously seals the devices, and the fabricated flexible devices have structural durability against bending. We have also shown that thermal lamination has an oriented growth effect, and the electrical characteristics of flexible organic field‐effect transistors did not degrade under a bending radius of 1 mm.

     

Influence of polymer dielectric surface energy on thin‐film transistor performance of solution‐processed triethylsilylethynyl anthradithiophene (TES‐ADT)

This study investigates the correlation between surface energy of polymer dielectrics and the film morphology, microstructure, and thin‐film transistor performance of solution‐processed 5,11‐bis(triethylsilylethynyl) anthradithiophene (TES‐ADT) films. The low surface energy polyimide (PI) dielectric induced large grains with strong X‐ray reflections for spin‐cast TES‐ADT films in comparison to high surface en‐ ergy poly(4‐vinyl phenol) (PVP) dielectric. Furthermore, thin‐film transistors based on spin‐cast TES‐ADT films on PI dielectric exhibited enhanced electrical performance, small hysteresis, and high stability under bias stress with carrier mobility as high as 0.43 cm²/Vs and a current on/off ratio of 10⁷. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium–gallium–zinc oxide thin film transistor, which adopts an elevated-metal metal–oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction.The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the backchannel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device(L = 2 μm). It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.     

Fabrication of 6,13‐bis(triisopropyl‐silylethynyl)–pentacene thin‐film transistors with the silver ink transfer method using a polymer stamp

We fabricated 6,13‐bis(triisopropylsilylethynyl)–pentacene (TIPS–pentacene) thin film transistors using a direct metal transfer method. Using different metals, such as Au and Ag ink, electrode patterns are formed from the relief region of the polymer mold. TIPS–pentacene TFTs using the Ag ink transfer method show a similar performance to those using the Au metal transfer method. This method has advantages over the Au metal transfer method because it does not require vacuum equipment and a dry etching process. The self‐assembled monolayer (SAM) treated device exhibits a carrier mobility of 9.5 × 10^–2 cm²/V · s, and an on/off ratio of 4.6 × 10⁴. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

非晶硅薄膜晶体管沟道中阈值电压及温度的分布

基于氢化非晶硅薄膜晶体管(a-Si:H TFT)沟道中陷阱态的双指数分布, 区分了带尾陷阱态和深能级陷阱态的特征温度.利用源端、漏端串联电阻及沟道电阻, 将源端和漏端特征长度与有源层接触长度、SiO₂/氢化非晶硅 (a-Si:H)界面陷阱态及a-Si:H薄膜内陷阱态联系起来. 由串联电阻上电流密度相等解出沟道势. 通过泊松方程和高斯定理 得出a-Si:H TFT沟道各点的阈值电压表达式, 结果表明 沟道中某一点的阈值电压随着该点与源端距离的增大而减小. 在此基础上, 研究了自加热效应引起沟道各点温度的变化, 结果显示a-Si:H TFT在自加热效应下, 从源端到漏端各点温度变化先增大后减小, 沟道中心的温度变化最大.     

铜-钼源漏电极对非晶氧化铟镓锌薄膜晶体管性能的改善

在铜(Cu)和非晶铟镓锌氧化物(a-IGZO)之间插入30 nm厚的钼(Mo)接触层, 制备了具有Cu-Mo源漏电极的a-IGZO薄膜晶体管(TFT). Mo接触层不仅能够抑制Cu与a-IGZO有源层之间的扩散, 而且提高了Cu电极与玻璃基底以及栅极绝缘层的结合强度. 制备的Cu-Mo结构TFT与纯Cu 结构TFT相比, 具有较高的迁移率(～9.26 cm²·V^-1·s^-1)、更短的电流传输长度(～0.2 μm)、更低的接触电阻(～1072 Ω)和有效接触电阻率(～1×10^-4Ω·cm²), 能够满足TFT 阵列高导互联的要求.     

高绒度掺硼氧化锌透明导电薄膜用作非晶硅太阳电池前电极的研究

将自行研制的具有优异陷光能力的掺硼氧化锌用作p-i-n型非晶硅太阳电池的前电极,并且将传统商业用U型掺氟二氧化锡作为对比电极.相比表面较为平滑的掺氟二氧化锡,掺硼氧化锌表面大类金字塔的绒面结构会在本征层生长过程中触发阴影效应,形成大量的高缺陷材料区和漏电沟道,进而恶化电池的开路电压和填充因子.在不修饰掺硼氧化锌表面形貌的情况下,通过调节非晶硅本征层的沉积温度来消弱高绒度表面形貌引起的这种不利影响,对应的电池开路电压和填充因子均出现提升.在仅有铝背电极的情况下,在本征层厚度为200 nm的情况下,以掺硼氧化锌为前电极的非晶硅太阳电池转换效率达7.34%(开路电压为0.9 V,填充因子为70.1%,短路电流密度11.7 mA/cm2).     

N2O处理对背沟刻蚀金属氧化物薄膜晶体管性能的影响

通过采用稀土元素镨掺杂铟锡锌氧化物半导体作为薄膜晶体管沟道层,成功实现了基于铝酸的湿法背沟道刻蚀薄膜晶体管的制备.研究了N₂O等离子体处理对薄膜晶体管背沟道界面的影响,对其处理功率和时间对器件性能的影响做了具体研究.结果表明,在一定的功率和时间处理下能获得良好的器件性能,所制备的器件具有良好的正向偏压热稳定性和光照条件下负向偏压热稳定性.高分辨透射电镜结果显示,该非晶结构的金属氧化物半导体材料可以有效抵抗铝酸的刻蚀,未发现明显的成分偏析现象.进一步的X射线光电能谱测试表明, N₂O等离子体处理能在界面处形成一个富氧、低载流子浓度的界面层.其一方面可以有效抵抗器件在沉积氧化硅钝化层时等离子体对背沟道的损伤;另一方面作为氢的钝化体,抑制了低能级施主态氢的产生,为低成本、高效的薄膜晶体管性能优化方式提供了重要参考.     

Quantitative evaluation method for electroluminescence images of a‐Si:H thin‐film solar modules

This work presents a method for extracting the absolute local junction voltage of a‐Si:H thin‐film solar cells and modules from electroluminescence (EL) images. It is shown that the electroluminescent emission of a‐Si:H devices follows a diode law with a radiative ideality factor n_r larger than one. We introduce an evaluation method that allows us to determine the absolute local junction voltage in cases of n_r > 1, while existing approaches rely on the assumption of n_r = 1. Furthermore, we find that the experimentally determined values of n_r vary from sample to sample. It is also explained why the derived radiative ideality factor is influenced by the spectral sensitivity of the camera system used in the experiment. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)