Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High‐performance In–Zn–O thin‐film transistors with a soluble processed ZrO2 gate insulator

Spin‐coated zirconium oxide films were used as a gate dielectric for low‐voltage, high performance indium zinc oxide (IZO) thin‐film transistors (TFTs). The ZrO₂ films annealed at 400 °C showed a low gate leakage current density of 2 × 10^–8 A/cm² at an electric field of 2 MV/cm. This was attributed to the low impurity content and high crystalline quality. Therefore, the IZO TFTs with a soluble ZrO₂ gate insulator exhibited a high field effect mobility of 23.4 cm²/V s, excellent subthreshold gate swing of 70 mV/decade and a reasonable I_on/off ratio of ～10⁶. These TFTs operated at low voltages (～3.0 V) and showed high drain current drive capability, enabling oxide TFTs with a soluble processed high‐k dielectric for use in backplane electronics for low‐power mobile display applications. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Control of electrical properties and gate bias stress stability in solution-processed a-IZO TFTs by Zr doping

Zr-doped indium zinc oxide (IZO) thin film transistors (TFTs) are fabricated via a solution process with different Zr doping ratios. The addition of Zr suppressed the carrier concentration in the IZO films, which was confirmed by Hall Effect measurements. As the amount of Zr was increased in the oxide active layer of TFTs, the subthreshold swing (S.S) reduced, the ON/OFF ratio improved, and the threshold voltage (V_th) shifted positively. Moreover, the starting points of the ON state for TFTs near the point zero gate voltage could be controlled by the addition of Zr. The 0.3% Zr-doped IZO TFT exhibited a high saturation mobility of 7.0 cm² V⁻¹ s⁻¹, ON/OFF ratio of 2.6 × 10⁶ and S.S of 0.57 V/decade compared the IZO TFT with 10.1 cm² V⁻¹ s⁻¹, 1.7 × 10⁶ and 0.75 V/decade. The Zr effect of the gate bias stability was examined. Zr-doped IZO TFTs were relatively unstable under a positive bias stress (PBS), whereas they showed good stability at a negative bias stress (NBS). The gate bias stability of the oxide TFTs were compared with the extracted parameters through a stretched-exponential equation. The characteristic trapping time under NBS of 0.3% Zr-doped IZO TFTs was improved from 8.3 × 10⁴ s for the IZO TFT to 3.1 × 10⁵ s.     

High‐mobility flexible thin‐film transistors with a low‐temperature zirconium‐doped indium oxide channel layer

Thin film transistors (TFTs) with zirconium‐doped indium oxide (ZrInO) channel layer were successfully fabricated on a flexible PEN substrate with process temperature of only 150 °C. The flexible ZrInO TFT exhibited excellent electrical performance with a saturation mobility of as high as 22.6 cm² V^–1 s^–1, a sub‐threshold swing of 0.39 V/decade and an on/off current ratio of 2.5 × 10⁷. The threshold voltage shifts were 1.89 V and ?1.56 V for the unpassivated flexible ZrInO TFT under positive and negative gate bias stress, respectively. In addition, the flexible ZrInO TFT was able to maintain the relatively stable performance at bending curvatures larger than 20 mm, but the off current increased apparently after bent at 10 mm. Detailed studies showed that Zr had an effect of suppress the free carrier generation without seriously distorting the In₂O₃ lattice. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Effect of antimony doping on the low‐temperature performance of solution‐processed indium oxide thin film transistors

The effects of antimony (Sb) doping on solution‐processed indium oxide (InO_x) thin film transistors (TFTs) were examined. The Sb‐doped InSbO TFT exhibited a high mobility, low gate swing, threshold voltage, and high I_ON/OFF ratio of 4.6 cm²/V s, 0.29 V/decade, 1.9 V, and 3 × 10⁷, respectively. The gate bias and photobias stability of the InSbO TFTs were also improved by Sb doping compared to those of InO_x TFTs. This improvement was attributed to the reduction of oxygen‐related defects and/or the existence of the lone‐pair s‐electron of Sb³⁺ in amorphous InSbO films. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

High performance Zn–Sn–O thin film transistors with Cu source/drain electrode

Zn–Sn–O (ZTO) thin film transistors (TFTs) were fabricated with a Cu source/drain electrode. Although a reasonably high mobility (μ_FE) of 13.2 cm²/Vs was obtained for the ZTO TFTs, the subthreshold gate swing (SS) and threshold voltage (V_th) of 1.1 V/decade and 9.1 V, respectively, were inferior. However, ZTO TFTs with Ta film inserted as a diffusion barrier, exhibited improved SS and V_th values of 0.48 V/decade and 3.0 V, respectively as well as a high μ_FE value of 18.7 cm²/Vs. The improvement in the Ta‐inserted device was attributed to the suppression of Cu lateral diffusion into the ZTO channel region. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

源漏电极的制备对氧化物薄膜晶体管性能的影响

本文采用钼-铝-钼(Mo/Al/Mo)叠层结构作为源漏电极,制备氧化铟锌(IZO)薄膜晶体管(TFT).研究了Mo/Al/Mo源漏电极中与IZO接触的Mo层溅射功率对TFT器件性能的影响.随着Mo层溅射功率的增加,器件开启电压(Von)负向移动,器件均匀性下降.通过X射线光电子能谱(XPS)深度剖析发现IZO/Mo界面有明显的扩散;当Mo层溅射功率减小时,扩散得到了抑制.制备的器件处于常关状态(开启电压为0.5 V,增强模式),不仅迁移率高(～13 cm2·V-1·s-1),而且器件半导体特性均匀.     

Selective floating gate non‐volatile paper memory transistor

Here we report the performance of a selective floating gate (V_GS) n‐type non‐volatile memory paper field‐effect transistor. The paper dielectric exhibits a spontaneous polarization of about 1 mCm^–2 and GIZO and IZO amorphous oxides are used respectively as the channel and the gate layers. The drain and source regions are based in continuous conductive thin films that promote the integration of fibres coated with the active semiconductor. The floating memory transistor writes, reads and erases the stored information with retention times above 14500 h, and is selective (for V_GS > 5 ± 0.1 V). That is, to erase stored information a symmetric pulse to the one used to write must be utilized, allowing to store in the same space different information. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Potential‐induced optimization of ultra‐thin rear surface passivated CIGS solar cells

Ultra‐thin Cu(In,Ga)Se₂ (CIGS) solar cells with an Al₂O₃ rear surface passivation layer between the rear contact and absorber layer frequently show a “roll‐over” effect in the J–V curve, lowering the open circuit voltage (V_OC), short circuit current (J_SC) and fill factor (FF), similar to what is observed for Na‐deficient devices. Since Al₂O₃ is a well‐known barrier for Na, this behaviour can indeed be interpreted as due to lack of Na in the CIGS absorber layer. In this work, applying an electric field between the backside of the soda lime glass (SLG) substrate and the SLG/rear‐contact interface is investi‐gated as potential treatment for such Na‐deficient rear surface passivated CIGS solar cells. First, an electrical field of +50 V is applied at 85 °C, which increases the Na concentration in the CIGS absorber layer and the CdS buffer layer as measured by glow discharge optical emission spectroscopy (GDOES). Subsequently, the field polarity is reversed and part of the previously added Na is removed. This way, the J –V curve roll‐over related to Na deficiency disappears and the V_OC (+25 mV), J_SC(+2.3 mA/cm²) and FF (+13.5% absolute) of the rear surface passivated CIGS solar cells are optimized. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Excellent passivation of thin silicon wafers by HF‐free hydrogen plasma etching using an industrial ICPECVD tool

In this work, hydrogen plasma etching of surface oxides was successfully accomplished on thin (～100 µm) planar n‐type Czochralski silicon wafers prior to intrinsic hydrogenated amorphous silicon [a‐Si:H(i)] deposition for heterojunction solar cells, using an industrial inductively coupled plasma‐enhanced chemical vapour deposition (ICPECVD) platform. The plasma etching process is intended as a dry alternative to the conventional wet‐chemical hydrofluoric acid (HF) dip for solar cell processing. After symmetrical deposition of an a‐Si:H(i) passivation layer, high effective carrier lifetimes of up to 3.7 ms are obtained, which are equivalent to effective surface recombination velocities of 1.3 cm s^–1 and an implied open‐circuit voltage (V_oc) of 741 mV. The passivation quality is excellent and comparable to other high quality a‐Si:H(i) passivation. High‐resolution transmission electron microscopy shows evidence of plasma‐silicon interactions and a sub‐nanometre interfacial layer. Using electron energy‐loss spectroscopy, this layer is further investigated and confirmed to be hydrogenated suboxide layers. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

P‐type tin‐oxide thin film transistors for blue‐light detection application

We reported the characteristics of p‐type tin‐oxide (SnO) thin film transistors (TFTs) upon illumination with visible light. Our p‐type TFT device using the SnO film as the active channel layer exhibits high sensitivity toward the blue‐light with a high light/dark read current ratio (I_light/I_dark) of 8.2 × 10³ at a very low driven voltage of <3 V. Since sensing of blue‐light radiation is very critical to our eyes, the proposed p‐type SnO TFTs with high sensitivity toward the blue‐light show great potential for future blue‐light detection applications.

     

High-density plasma etching of indium-zinc oxide films in Ar/Cl2 and Ar/CH4/H2 chemistries

The dry etching characteristics of transparent and conductive indium-zinc oxide (IZO) films have been investigated using an inductively coupled high-density plasma. While the Cl₂-based plasma mixture showed little enhancement over physical sputtering in a pure argon atmosphere, the CH₄/H₂/Ar chemistry produced an increase of the IZO etch rate. On the other hand, the surface morphology of IZO films after etching in Ar and Ar/Cl₂ discharges is smooth, whereas that after etching in CH₄/H₂/Ar presents particle-like features resulting from the preferential desorption of In- and O-containing products. Etching in CH₄/H₂/Ar also produces formation of a Zn-rich surface layer, whose thickness (∼40 nm) is well-above the expected range of incident ions in the material (∼1 nm). Such alteration of the IZO layer after etching in CH₄/H₂/Ar plasmas is expected to have a significant impact on the transparent electrode properties in optoelectronic device fabrication.     

微晶硅薄膜晶体管稳定性研究

对有源区处于结构过渡区的微晶硅底栅薄膜晶体管，测试其偏压衰退特性时，观察到一种“自恢复”的衰退现象.当栅和源漏同时施加10 V的偏压时，测试其源-漏电流随时间的变化，发现源-漏电流先衰减、而后又开始恢复上升的反常现象.而当采用栅压为10 V、源-漏之间施加零偏压的模式时，源-漏电流随时间呈先是几乎指数式下降、随之是衰退速度减缓的正常衰退趋势.就此现象进行了初步探讨. 关键词： 过渡区硅材料 微晶硅薄膜晶体管 稳定性 自恢复衰退     

Surface passivation of phosphorus‐diffused n+‐type emitters by plasma‐assisted atomic‐layer deposited Al2O3

In recent years Al₂O₃ has received tremendous interest in the photovoltaic community for the application as surface passivation layer for crystalline silicon. Especially p‐type c‐Si surfaces are very effectively passivated by Al₂O₃, including p‐type emitters, due to the high fixed negative charge in the Al₂O₃ film. In this Letter we show that Al₂O₃ prepared by plasma‐assisted atomic layer deposition (ALD) can actually provide a good level of surface passivation for highly doped n‐type emitters in the range of 10–100 Ω/sq with implied‐V_oc values up to 680 mV. For n‐type emitters in the range of 100–200 Ω/sq the implied‐V_oc drops to a value of 600 mV for a 200 Ω/sq emitter, indicating a decreased level of surface passivation. For even lighter doped n‐type surfaces the passivation quality increases again to implied‐V_oc values well above 700 mV. Hence, the results presented here indicate that within a certain doping range, highly doped n‐ and p‐type surfaces can be passivated simultaneously by Al₂O₃. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

High‐performance a‐Si1–xOx:H/c‐Si heterojunction solar cells realized by the a‐Si:H/a‐Si1–xOx:H stack buffer layer

We used amorphous silicon oxide (a‐Si_1–xO_x:H) and microcrystalline silicon oxide (µc‐Si_1–xO_x:H) as buffer layer and p‐type emitter layer, respectively, in n‐type silicon hetero‐junction (SHJ) solar cells. We proposed to insert a thin (2 nm) intrinsic amorphous silicon (a‐Si:H) thin film between the thin (2.5 nm) a‐Si_1–xO_x:H buffer layer and the p‐layer to form a stack buffer layer of a‐Si:H/a‐Si_1–xO_x:H. As a result, a high open‐circuit voltage (V_OC) and a high fill factor (FF) were obtained at the same time. Finally, a high efficiency of 19.0% (J_SC = 33.46 mA/cm², V_OC = 738 mV, FF = 77.0%) was achieved on a 100 μm thick polished wafer using the stack buffer layer.

     

Efficient interdigitated back‐contacted silicon heterojunction solar cells

We present back‐contacted amorphous/crystalline silicon heterojunction solar cells (IBC‐SHJ) on n‐type substrates with fill factors exceeding 78% and high current densities, the latter enabled by a SiN_x /SiO₂ passivated phosphorus‐diffused front surface field. V_oc calculations based on carrier lifetime data of reference samples indicate that for the IBC architecture and the given amorphous silicon layer qualities an emitter buffer layer is crucial to reach a high V_oc, as known for both‐side contacted silicon heterojunction solar cells. A back surface field buffer layer has a minor influence. We observe a boost in solar cell V_oc of 40 mV and a simultaneous fill factor reduction introducing the buffer layer. The aperture‐area efficiency increases from 19.8 ± 0.4% to 20.2 ± 0.4%. Both, efficiencies and fill factors constitute a significant improvement over previously reported values. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

A study of electrical enhancement of polycrystalline MgZnO/ZnO bi-layer thin film transistors dependence on the thickness of ZnO layer

A polycrystalline MgZnO/ZnO bi-layer was deposited by using a RF co-magnetron sputtering method and the MgZnO/ZnO bi-layer TFTs were fabricated on the thermally oxidized silicon substrate. The performances with varying the thickness of ZnO layer were investigated. In this result, the MgZnO/ZnO bi-layer TFTs which the content of Mg is about 2.5 at % have shown the enhancement characteristics of high mobility (6.77–7.56 cm² V⁻¹ s⁻¹) and low sub-threshold swing (0.57–0.69 V decade⁻¹) compare of the ZnO single layer TFT (μ_FE = 5.38 cm² V⁻¹ s⁻¹; S.S. = 0.86 V decade⁻¹). Moreover, in the results of the positive bias stress, the ΔV_on shift (4.8 V) of MgZnO/ZnO bi-layer is the 2 V lower than ZnO single layer TFT (ΔV_on = 6.1 V). It reveals that the stability of the MgZnO/ZnO bi-layer TFT enhanced compared to that of the ZnO single layer TFT.     

Bias‐driven super‐insulating state in prismane single‐molecule contacts

Quantum transport in a single‐molecule contact made of a prismane cluster C₈ attached to quasi‐one‐dimensional gold (100) electrodes is calculated using the ab initio methodology based on the density‐functional theory and the nonequilibrium Green's functions formalism. Varying the junction length L we calculate the length dependence of the zero‐bias conductance G (L) and, for a set of the interelectrode distances, the current–voltage (I –V) characteristics. It is shown that the G (L) dependence is strongly nonmonotonic with a sharp dip at some value of L. With increase in L, the I –V curves change their shape from monotonic curves to curves with a negative differential resistance area and, for a larger L, the junction exhibits the super‐insulating state, i.e., within some applied bias voltage range the current through the junctions is about two orders of magnitude less than the current outside this bias range. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Au/TiO2 nanorod‐based Schottky‐type UV photodetectors

TiO₂ nanorods (NRs) were synthesized on fluorine‐doped tin oxide (FTO) pre‐coated glass substrates using hydrothermal growth technique. Scanning electron microscopy studies have revealed the formation of vertically‐aligned TiO₂ NRs with length of ～2 µm and diameter of 110–128 nm, homogenously distributed over the substrate surface. 130 nm thick Au contacts using thermal evaporation were deposited on the n‐type TiO₂ NRs at room temperature for the fabrication of NR‐based Schottky‐type UV photodetectors. The fabricated Schottky devices functioned as highly sensitive UV photodetectors with a peak responsivity of 134.8 A/W (λ = 350 nm) measured under 3 V reverse bias. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Tuning of the open‐circuit voltage by wide band‐gap absorber and doped layers in thin film silicon solar cells

We present an experimental study combined with computer simulations on the effects of wide band‐gap absorber and window layers on the open‐circuit voltage (V_oc) in single junction thin film silicon solar cells. The quantity ΔE_p, taking as the difference between the band gap and the activation energy in ?p? layer, is treated as a measure of the p‐layer properties and shows a linear relation with V_oc over a range of 100 mV with a positive slope of around 430 mV/eV. Two limiting mechanisms of V_oc are identified: the built‐in potential at lower ΔE_p and the band gap of the absorber layer at higher ΔE_p. The results of the experimental findings are confirmed by computer simulations. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)