Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

In this work, the trap-assisted tunneling(TAT) mechanism is modeled as a two-step physical process for charge trapping memory(CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.     

The influence of thermally assisted tunneling on the performance of charge trapping memory

We evaluate the influence of the thermally assisted tunneling (TAT) mechanism on charge trapping memory (CTM) cell performance by numerical simulation, and comprehensively analyse the effects of the temperature, trap depth, distribution of trapped charge, gate voltage and parameters of TAT on erasing/programming speed and retention performance. TAT is an indispensable mechanism in CTM that can increase the detrapping probability of trapped charge. Our results reveal that the TAT effect causes the sensitivity of cell performance to temperature and it could affect the operational speed, especially for the erasing operation. The results show that the retention performance degrades compared with when the TAT mechanism is ignored.     

Performance improvement of charge trap flash memory by using a composition-modulated high-k trapping layer

A composition-modulated （HfO2）x（Al2O3）1-x charge trapping layer is proposed for charge trap flash memory by controlling the A1 atom content to form a peak and valley shaped band gap. It is found that the memory device using the composition-modulated （HfO2）x（Al2O3）l-x as the charge trapping layer exhibits a larger memory window of 11.5 V, improves data retention even at high temperature, and enhances the program/erase speed. Improvements of the memory characteristics are attributed to the special band-gap structure resulting from the composition-modulated trapping layer. Therefore, the composition-modulated charge trapping layer may be useful in future nonvolatile flash memory device application.     

Carriers recombination processes in charge trapping memory cell by simulation

We have evaluated the effects of recombination processes in a charge storage layer, either between trapped electrons and trapped holes or between trapped carriers and free carriers, on charge trapping memory cell＇s performances by numerical simulation. Recombination is an indispensable mechanism in charge trapping memory. It helps charge convert process between negative and positive charges in the charge storage layer during charge trapping memory programming/erasing operation. It can affect the speed of programming and erasing operations.     

The charge storage characteristics of ZrO2 nanocrystallite-based charge trap nonvolatile memory

ZrO2 nanocrystallite-based charge trap flash memory capacitors incorporating a(ZrO2)0.6(SiO2)0.4 pseudobinary high-k oxide film as the charge trapping layer were prepared and investigated.The precipitation reaction in the charge trapping layer,forming ZrO2 nanocrystallites during rapid thermal annealing,was investigated by transmission electron microscopy and X-ray diffraction.It was observed that a ZrO2 nanocrystallite-based memory capacitor after post-annealing at 850℃ for 60s exhibits a maximum memory window of about 6.8V,good endurance and a low charge loss of ～25% over a period of 10 years(determined by extrapolating the charge loss curve measured experimentally),even at 85℃.Such 850℃-annealed memory capacitors appear to be candidates for future nonvolatile flash memory device applications.     

Silicon surface passivation by atomic‐layer‐deposited Al2O3 facilitated in situ by the combination of H2O and O3 as reactants

We investigate the effect of O₃ and H₂O oxidant pre‐pulse prior to Al₂O₃ atomic layer deposition for Si surface passivation. Interfacial oxide SiO_x formed by the O₃ pre‐pulse is more beneficial than that by H₂O to a high level of surface passivation. The passivation of thinner H₂O–Al₂O₃ films is more improved by this O₃ pre‐pulse. O₃ pre‐pulse for 10 nm H₂O–Al₂O₃ reduces saturation current density in boron emitter to 18 fA cm^–2 by a factor of 1.7. Capacitance–voltage measurements reveal this interfacial oxide plays a role of decreasing interface trap density without detrimental effect to negative charge density of Al₂O₃. (© 2014 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Effective silicon surface passivation by atomic layer deposited Al2O3/TiO2 stacks

In this work atomic layer deposition of Al₂O₃ and TiO₂ has been used to obtain dielectric stacks for passivation of silicon surfaces. Our experiments on n‐ and p‐type silicon wafers deposited by thin Al₂O₃/TiO₂ stacks show that a considerably improved passivation is obtained compared to the Al₂O₃ single layer. For Al₂O₃ films thinner than 20 nm the emitter saturation current density decreases with increasing TiO₂ thickness. Especially the passivation of ultrathin (～5 nm) Al₂O₃ is very effectively enhanced by TiO₂ due to a decreased interface defect density as well as an increased fixed negative charge in the stacks. Hence, the thin Al₂O₃/TiO₂ stacks developed in this work can be used as a passivation coating for Si‐based solar cells. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

A12o3钝化及其在晶硅太阳电池中的应用

介绍了A1203的材料性质及其原子层沉积制备方法,详细阐述了该材料的钝化机制（化学钝化和场效应钝化）,并从薄膜厚度、热稳定性及叠层钝化等角度阐释其优化方案．概述了Al203钝化在晶体硅太阳电池中的应用,主要包括钝化发射极及背面局部扩散电池和钝化发射极及背表面电池．最后,对A1203钝化工艺的未来研究方向和大规模的工业应用进行了展望．     

Influences of different oxidants on characteristics of La_2O_3/Al_2O_3 nanolaminates deposited by atomic layer deposition

A comparative study of two kinds of oxidants(H_2O and O_3) with the combination of two metal precursors(TMA and La(~iPrCp)_3) for atomic layer deposition(ALD) La_2O_3/Al_2O_3 nanolaminates is carried out. The effects of different oxidants on the physical properties and electrical characteristics of La_2O_3/Al_2O_3 nanolaminates are studied. Initial testing results indicate that La_2O_3/Al_2O_3 nanolaminates could avoid moisture absorption in the air after thermal annealing. However, moisture absorption occurs in H_2O-based La_2O_3/Al_2O_3 nanolaminates due to the residue hydroxyl/hydrogen groups during annealing. As a result, roughness enhancement, band offset variation, low dielectric constant and poor electrical characteristics are measured because the properties of H_2O-based La_2O_3/Al_2O_3 nanolaminates are deteriorated. Addition thermal annealing effects on the properties of O_3-based La_2O_3/Al_2O_3 nanolaminates indicate that O_3 is a more appropriate oxidant to deposit La_2O_3/Al_2O_3 nanolaminates for electron devices application.     

Plasma enhanced atomic layer deposition of gallium oxide on crystalline silicon: demonstration of surface passivation and negative interfacial charge

Herein we report on the passivation of crystalline silicon by gallium oxide (Ga₂O₃) using oxygen plasma as the oxidizing reactant in an atomic layer deposition (ALD) process. Excess carrier lifetimes of 2.1 ms have been measured on 1.75 Ω cm p‐type silicon, from which a surface recombination current density J₀ of 7 fA cm^–2 is extracted. From high frequency capacitance‐voltage (HF CV) measurements it is shown that, as in the case of Al₂O₃, the presence of a high negative charge density Q_tot/q of up to –6.2 × 10¹² cm^–2 is one factor contributing to the passivation of silicon by Ga₂O₃. Defect densities at midgap on the order of ～5 × 10¹¹ eV^–1 cm^–2 are extracted from the HF CV data on samples annealed at 300 °C for 30 minutes in a H₂/Ar ambient, representing an order of magnitude reduction in the defect density compared to pre‐anneal data. Passivation of a boron‐diffused p⁺ surface (96 Ω/□) is also demonstrated, resulting in a J₀ of 52 fA cm^–2. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

原子层沉积Al2O3/n-GaN MOS结构的电容特性

利用原子层沉积技术制备了具有圆形透明电 极的Ni/Au/Al₂O₃/n-GaN金属-氧化物-半导体结构, 研究了紫外光照对样品电容特性及深能级界面态的影响, 分析了非理想样品积累区电容随偏压增加而下降的物理起源. 在无光照情形下, 由于极长的电子发射时间与极慢的少数载流子热产生速率, 样品的室温电容-电压扫描曲线表现出典型的深耗尽行为, 且准费米能级之上占据深能级界面态的电子状态保持不变. 当器件受紫外光照射时, 半导体耗尽层内的光生空穴将复合准费米能级之上的深能级界面态电子, 同时还将与氧化层内部的深能级施主态反应. 非理想样品积累区电容的下降可归因于绝缘层漏电导的急剧增大, 其诱发机理可能是与氧化层内的缺陷态及界面质量有关的“charge-to-breakdown”过程. 关键词： 原子层沉积 2O₃/n-GaN')" href="#">Al₂O₃/n-GaN 金属-氧化物-半导体结构 电容特性     

热原子层沉积氧化铝对硅的钝化性能及热稳定性

原子层沉积氧化铝已经成为应用于钝化发射极和背面点接触（PERC）型晶硅太阳能电池优异的钝化材料．对于基于丝网印刷技术的太阳能电池,钝化材料的钝化效果及其热稳定性是非常重要的．本文在太阳能级硅片上用热原子层沉积设备制备了20nm和30nm的氧化铝,少子寿命测试结果显示初始沉积的氧化铝薄膜具有一定的钝化效果,在退火后可达到100μs以上,相当于硅表面复合速度小于100cm／s．经过制备传统晶硅太阳能电池的烧结炉后,少子寿命能够保持在烧结前的一半以上,可应用于工业PERC型电池的制备．通过电子显微镜观察到了较厚的氧化铝薄膜有气泡,解释了30nm氧化铝比20nm氧化铝钝化性能和稳定性更差的异常表现．     

Performance and reliability improvement of La_2O_3/Al_2O_3 nanolaminates using ultraviolet ozone post treatment

La-based binary or ternary compounds have recently attracted a great deal of attention as a potential candidate to replace the currently used Hf-based dielectrics in future transistor and capacitor devices for sub-22 generation. However, the hygroscopic nature of La₂O₃ hampers its application as dielectrics in electron devices. To cope with this challenge, ultraviolet (UV) ozone post treatment is proposed to suppress the moisture absorption in the H₂O-based atomic layer deposition (ALD) La₂O₃/Al₂O₃ nanolaminates which is related to the residual hydroxyl/hydrogen groups after annealing. The x-ray photoelectron spectroscopy (XPS) and conductive atomic force microscopy (AFM) results indicate that the moisture absorption of the H₂O-based ALD La₂O₃/Al₂O₃ nanolaminates is efficiently suppressed after 600 ℃ annealing, and the electrical characteristics are greatly improved.     

Stacked and nanolaminated Al2O3/TiO2 for surface passivation and encapsulation of silicon

Silicon solar cells passivated with Al₂O₃ require a capping layer that protects the passivation layer from humidity because of sensitivity of Al₂O₃ to moisture. Al₂O₃/TiO₂ stacks obtained by atomic layer deposition have been known to provide a high level of passivation layers because of their excellent field‐effect passivation. In this work, degradation of this Al₂O₃/TiO₂ stack, when exposed to humidity, is examined, and an attempt is made for a humidity‐resistant encapsulation layer by adding Al₂O₃/TiO₂ nanolaminates that can be deposited in‐situ without breaking vacuum. Placing the nanolaminate on top of the TiO₂ and Al₂O₃ stack is found to lead to almost no degradation even after 10 days of humidity exposure. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Crystalline silicon surface passivation investigated by thermal atomic-layer-deposited aluminum oxide

Atomic-layer-deposited(ALD) aluminum oxide(Al_2O_3) has demonstrated an excellent surface passivation for crystalline silicon(c-Si) surfaces, as well as for highly boron-doped c-Si surfaces. In this paper, water-based thermal atomic layer deposition of Al_2O_3 films are fabricated for c-Si surface passivation. The influence of deposition conditions on the passivation quality is investigated. The results show that the excellent passivation on n-type c-Si can be achieved at a low thermal budget of 250℃ given a gas pressure of 0.15 Torr. The thickness-dependence of surface passivation indicates that the effective minority carrier lifetime increases drastically when the thickness of Al_2O_3 is larger than 10 nm. The influence of thermal post annealing treatments is also studied. Comparable carrier lifetime is achieved when Al_2O_3 sample is annealed for 15 min in forming gas in a temperature range from 400℃ to 450℃. In addition, the passivation quality can be further improved when a thin PECVD-SiN_x cap layer is prepared on Al_2O_3, and an effective minority carrier lifetime of2.8 ms and implied Voc of 721 mV are obtained. In addition, several novel methods are proposed to restrain blistering.     

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In-Ga-Zn-O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO₂ heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 ℃. Compared to a single p-SnO or n-SnO₂ charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO₂/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at -8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO₂, and the formation of a built-in electric field in the heterojunction.     

Low‐thermal budget flash light annealing for Al2O3 surface passivation

This value is achieved due to a very low interface trap density of below 10¹⁰ eV^–1 cm^–2 and a fixed charge density of (2–3) × 10¹² cm^–2. In contrast, plasma ALD‐grown Al₂O₃ layers only reach carrier lifetimes of about 1 ms. This is mainly caused by a more than 10 times higher density of interface traps, and thus, inferior chemical passivation. The strong influence of the deposition parameters is explained by the limitation of hydrogen transport in Al₂O₃ during low‐thermal budget annealing. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)