Organic light‐emitting transistors with voltage‐tunable lit area and full channel illumination

Organic light‐emitting transistors (OLETs) are multifunctional optoelectronic devices that hold great promise for a variety of applications, including flat panel displays, integrated light sources for sensing and optical communication systems. The narrow illumination area within the device channel is considered intrinsic to the device architecture and is a severe technological drawback for all those applications where a controlled, wide and homogeneous emission area is required. Here it is shown that not only the position but also the extension of the emission area is voltage‐tunable, and the entire channel of the transistor can be homogeneously illuminated. The modeling of the exciton distribution within the channel at the different bias conditions coupled to the modeling of the device emission profile highlights that excitons are spread through the entire channel width and across the bulk of the central emission layer of the p‐channel/emitter/n‐channel trilayer active heterostructure.     

Frontispiece: Organic light‐emitting transistors with voltage‐tunable lit area and full channel illumination

Organic light‐emitting transistors (OLETs) are multifunctional optoelectronic devices that hold great promise for a variety of applications, including flat panel displays, integrated light sources for sensing and optical communication systems. The narrow illumination area within the device channel is considered intrinsic to the device architecture and is a severe technological drawback for all those applications where a controlled, wide and homogeneous emission area is required. S. Toffanin et al. (pp. 1011–1019) show that not only the position but also the extension of the emission area is voltage‐tunable, and the entire channel of the transistor can be homogeneously illuminated. The modeling of the exciton distribution within the channel at the different bias conditions coupled to the modeling of the device emission profile highlights that excitons are spread through the entire channel width and across the bulk of the central emission layer of the p‐channel/emitter/n‐channel trilayer active heterostructure.     

Three-dimensional vertical ZnO transistors with suspended top electrodes fabricated by focused ion beam technology

Three-dimensional(3D)vertical architecture transistors represent an important technological pursuit,which have distinct advantages in device integration density,operation speed,and power consumption.However,the fabrication processes of such 3D devices are complex,especially in the interconnection of electrodes.In this paper,we present a novel method which combines suspended electrodes and focused ion beam(FIB)technology to greatly simplify the electrodes interconnection in 3D devices.Based on this method,we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al₂O₃ gate-oxide both grown by atomic layer deposition.Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires,which avoid cumbersome steps in the traditional 3D structure fabrication technology.Both single pillar and arrays devices show well behaved transfer characteristics with an Ion/Ioff current ratio greater than 106 and a low threshold voltage around 0 V.The ON-current of the 2×2 pillars vertical channel transistor was 1.2μA at the gate voltage of 3 V and drain voltage of 2 V,which can be also improved by increasing the number of pillars.Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption.     

Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface

Tremendous progress in information technology has been made possible by the development and optimization of metal oxide semiconductor field effect transistor (MOSFET) devices. For the last three decades, the dimensions of the devices have been scaled down and the complexity of the integrated circuits increased according to Moore’s law. Further scaling of the devices has been predicted by the international technology roadmap for semiconductors (ITRS). To meet the future technological requirements, much effort has been expended on increasing the capabilities of MOSFETs. Both new materials and new designs have been introduced to maintain device scaling. Most new designs were improvements of the normal planar design of the device, such as SOI and ultrathin body devices. In so-called FinFET structures, current flows through a thin silicon fin and is controlled by two gates in parallel on both sides of the fin. Vertical MOSFET devices represent a new category. In these structures the planar arrangement of the source gate and drain is turned through 90° so that they are positioned on top of each other and the current flow is perpendicular to the surface. By utilizing the 3rd dimension, the channel length can be adjusted by layer deposition and thus dispensing with advanced (and expensive) lithography. Furthermore, depending on the application, the vertical designs require less space than planar ones so that it is possible to increase integration density. The present paper gives a review of vertical MOSFET devices with current flow perpendicular to the surface. PACS 85.30     

Transport properties and device-design of Z-shaped MoS2 nanoribbon planar junctions

Based on MoS₂ nanoribbons, metal-semiconductor-metal planar junction devices were constructed. The electronic and transport properties of the devices were studied by using density function theory (DFT) and nonequilibrium Green's functions (NEGF). It is found that a band gap about 0.4 eV occurs in the planar junction. The electron and hole transmissions of the devices are mainly contributed by the Mo atomic orbitals. The electron transport channel is located at the edge of armchair MoS₂ nanoribbon, while the hole transport channel is delocalized in the channel region. The I-V curve of the two-probe device shows typical transport behavior of Schottky barrier, and the threshold voltage is of about 0.2 V. The field effect transistors (FET) based on the planar junction turn out to be good bipolar transistors, the maximum current on/off ratio can reach up to 1 × 10⁴, and the subthreshold swing is 243 mV/dec. It is found that the off-state current is dependent on the length and width of the channel, while the on-state current is almost unaffected. The switching performance of the FET is improved with increasing the length of the channel, and shows oscillation behavior with the change of the channel width.     

Junctionless nanowire transistor fabricated with high mobility Ge channel

The junctionless nanowire metal–oxide–semiconductor field‐effect transistor (JNT) has recently been proposed as an alternative device for sub‐20‐nm nodes. The JNT architecture eliminates the need for forming PN junctions, resulting in simple processing and competitive electrical characteristics. In order to further boost the drive current, alternative channel materials such as III–V and Ge, have been proposed. In this Letter, JNTs with Ge channels have been fabricated by a CMOS‐compatible top–down process. The transistors exhibit the lowest subthreshold slope to date for JNT with Ge channels. The devices with a gate length of 3 μm exhibit a subthreshold slope (SS) of 216 mV/dec with an I_ON/I_OFF current ratio of 1.2 × 10³ at V_D = –1 V and drain‐induced‐barrier lowering (DIBL) of 87 mV. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

A new method to invert top-gate organic field-effect transistors for Kelvin probe investigations

In this contribution, we present a technique which allows for the investigation of the local channel potentials of a poly(3-hexylthiophene) (P3HT)-based top-gate field-effect transistor. Usually it is impossible to measure the channel potentials of a top-gate transistor with a Kelvin probe force microscope (KPFM) due to the electrical shielding of the top-gate or the weak capacitive coupling of the tip through the thick substrate to the channel. However, by depositing the entire device on a water solvable polyvinyl alcohol layer, devices can be completely detached from the substrate, creating a free-standing functioning organic field-effect transistor (OFET). After detaching, it is possible to laminate the inverted device on another substrate. This method grants access to the usually hidden channel of the top-gate OFET, and therefore KPFM measurements can be performed.     

Erbium‐doped integrated waveguide amplifiers and lasers

Erbium‐doped fiber devices have been extraordinarily successful due to their broad optical gain around 1.5–1.6 µm. Er‐doped fiber amplifiers enable efficient, stable amplification of high‐speed, wavelength‐division‐multiplexed signals, thus continue to dominate as part of the backbone of longhaul telecommunications networks. At the same time, Er‐doped fiber lasers see many applications in telecommunications as well as in biomedical and sensing environments. Over the last 20 years significant efforts have been made to bring these advantages to the chip level. Device integration decreases the overall size and cost and potentially allows for the combination of many functions on a single tiny chip. Besides technological issues connected to the shorter device lengths and correspondingly higher Er concentrations required for high gain, the choice of appropriate host material as well as many design issues come into play in such devices. In this contribution the important developments in the field of Er‐doped integrated waveguide amplifiers and lasers are reviewed and current and future potential applications are explored. The vision of integrating such Er‐doped gain devices with other, passive materials platforms, such as silicon photonics, is discussed.     

Study on a novel vertical enhancement-mode Ga2O3 MOSFET with FINFET structure

A novel enhanced mode(E-mode)Ga₂O₃ metal-oxide-semiconductor field-effect transistor(MOSFET)with vertical FINFET structure is proposed and the characteristics of that device are numerically investigated.It is found that the concentration of the source region and the width coupled with the height of the channel mainly effect the on-state characteristics.The metal material of the gate,the oxide material,the oxide thickness,and the epitaxial layer concentration strongly affect the threshold voltage and the output currents.Enabling an E-mode MOSFET device requires a large work function gate metal and an oxide with large dielectric constant.When the output current density of the device increases,the source concentration,the thickness of the epitaxial layer,and the total width of the device need to be expanded.The threshold voltage decreases with the increase of the width of the channel area under the same gate voltage.It is indicated that a set of optimal parameters of a practical vertical enhancement-mode Ga₂O₃ MOSFET requires the epitaxial layer concentration,the channel height of the device,the thickness of the source region,and the oxide thickness of the device should be less than 5×10¹⁶ cm^-3,less than 1.5μm,between 0.1μm-0.3μm and less than 0.08μm,respectively.     

Positive gate bias stress-induced hump-effect in elevated-metal metal-oxide thin film transistors

Under the action of a positive gate bias stress, a hump in the subthreshold region of the transfer characteristic is observed for the amorphous indium–gallium–zinc oxide thin film transistor, which adopts an elevated-metal metal–oxide structure. As stress time goes by, both the on-state current and the hump shift towards the negative gate-voltage direction.The humps occur at almost the same current levels for devices with different channel widths, which is attributed to the parasitic transistors located at the channel width edges. Therefore, we propose that the positive charges trapped at the backchannel interface cause the negative shift, and the origin of the hump is considered as being due to more positive charges trapped at the edges along the channel width direction. On the other hand, the hump-effect becomes more significant in a short channel device(L = 2 μm). It is proposed that the diffusion of oxygen vacancies takes place from the high concentration source/drain region to the intrinsic channel region.     

Resonant tunneling field-effect transistors

We report an experimental project to incorporate double-barrier tunnel structures into three-terminal devices. These devices have the negative-differential-resistance (NDR) features of the double barrier, and the added flexibility of a third controlling electrode. One way to make such a device involves the series combination of a double-barrier tunnel structure with a field-effect transistor. We have realized this concept in two types of devices, using samples grown by metalorganic chemical vapor deposition. The devices consist of a GaAsAl_xGa_1−xAs double-barrier tunneling heterostructure, the current through which is controlled by either an integrated vertical field-effect transistor or a planar metal-semiconductor field effect transistor. The voltage location and peak-to-valley current ratio of the NDR present in the source-drain circuit can be modulated with gate voltage. Experimental results for four samples are presented.     

AlGaN/GaN双异质结F注入增强型高电子迁移率晶体管

理论模拟了不同GaN沟道厚度的双异质结(AlGaN/GaN/AlGaN/GaN)材料对高电子迁移率晶体管(HEMT)特性的影响,并模拟了不同F注入剂量下用该材料制作的增强型器件的特性差异.采用双异质结材料,结合F注入工艺成功地研制出了较高正向阈值电压的增强型HEMT器件.实验研究了三种GaN沟道厚度制作的增强型器件直流特性的差异,与模拟结果进行了对比验证.采用降低的F注入等离子体功率,减小了等离子体处理工艺对器件沟道迁移率的损伤,研制出的器件未经高温退火即实现了较高的跨导和饱和电流特性.对14 nm GaN沟道厚度的器件进行了阈值电压温度稳定性和栅泄漏电流的比较研究,并且分析了双异质结器件的漏致势垒降低效应.     

Field-effect transistor with recombinant potassium channels: fast and slow response by electrical and chemical interactions

Electrical interfacing of semiconductor devices with ion channels is the basis for a development of neuroelectronic systems and of cell-based biospecific electronic sensors. To elucidate the mechanism of cell–chip coupling, we studied the voltage-gated potassium channel Kv1.3 in HEK 293 cells on field-effect transistors in silicon with a metal-free gate of silicon dioxide. Upon intracellular depolarization there is a positive change of the effective extracellular voltage on the transistor with an amplitude that correlates with the gating of Kv1.3 channels, but with a dynamics that is far slower than channel gating. After repolarization there is a fast negative change of the transistor signal followed by a slow relaxation dynamics without any membrane current. To rationalize the involved transistor response, we propose a concept that combines the electrodiffusion of ions in the cell–chip junction with selective ion binding in the electrical double layer of silicon dioxide. The model implies (i) an electrical charging and discharging of the cell–chip capacitance within a microsecond, (ii) a changing K⁺ concentration in the cell–chip junction within a millisecond and (iii) a changing adsorption of K⁺ and Na⁺ ions within tens of milliseconds. The total transistor signal is a superposition of the changed electrical potential in the extracellular space between cell and chip and of the changed surface potential at the chip surface. PACS 73.40.Mr; 82.45.Vp; 85.30.Tv; 87.16.Uv; 87.19.Nn     

绝缘体上硅金属氧化物半导体场效应晶体管中辐射导致的寄生效应研究

基于⁶⁰Co γ射线源研究了总剂量辐射对绝缘体上硅（silicon on insulator,SOI）金属氧化物半导体场效应晶体管器件的影响.通过对比不同尺寸器件的辐射响应,分析了导致辐照后器件性能退化的不同机制.实验表明：器件的性能退化来源于辐射增强的寄生效应;浅沟槽隔离（shallow trench isolation,STI）寄生晶体管的开启导致了关态漏电流随总剂量呈指数增加,直到达到饱和;STI氧化层的陷阱电荷共享导致了窄沟道器件的阈值电压漂移,而短沟道器件的阈值电压漂移则来自于背栅阈值耦合;在同一工艺下,尺寸较小的器件对总剂量效应更敏感.探讨了背栅和体区加负偏压对总剂量效应的影响,SOI器件背栅或体区的负偏压可以在一定程度上抑制辐射增强的寄生效应,从而改善辐照后器件的电学特性.     

HOT-CARRIER GENERATION MECHANISM AND HOT-CARRIER EFFECT IMMUNITY IN DEEP-SUB-MICRON GROOVED-GATE PMOSFETS

Based on the hydrodynamic energy transport model, immunity from the hot-carrier effect in deep-sub-micron grooved-gate p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) is analysed. The results show that hot carriers generated in grooved-gate PMOSFETs are much smaller than those in planar ones, especially for the case of channel lengths lying in the deep-sub-micron and super deep-sub-micron regions. Then, the hot-carrier generation mechanism and the reason why grooved-gate MOS devices can suppress the hot-carrier effect are studied from the viewpoint of physical mechanisms occurring in devices. It is found that the highest hot-carrier generating rate is at a medium gate bias voltage in three stress areas, similar to conventional planar devices. In deep-sub-micron grooved-gate PMOSFETs, the hot-carrier injection gate current is still composed mainly of the hot-electron injection current, and the hole injection current becomes dominant only at an extremely high gate voltage. In order to investigate other influences of the hot-carrier effect on the device characteristics, the degradation of the device performance is studied for both grooved-gate and planar devices at different interface states. The results show that the drift of the device electrical performance induced by the interface states in grooved-gate PMOSFETs is far larger than that in planar devices.     

A low subthreshold swing tunneling field effect transistor for next generation low power CMOS applications

We propose a low subthreshold swing transistor architecture called Negative Capacitance Single Gate Silicon-On-Insulator Tunneling Field Effect Transistor (NC-SG-SOI-TFET) and present an analytical model to characterize its performance. Electrostatic potential distribution and electric field intensity in the channel region are obtained by solving the Poisson equation, and the drain current is calculated using the band-to-band carrier generation rate. An additional layer of ferroelectric oxide is used to obtain the negative capacitance. Effect of ferroelectric oxide is incorporated using one-dimensional Landau formalism. Through two dimensional theoretical analysis, we show that the proposed device has superior performance over traditional TFETs in terms of subthreshold swing and short channel effects. For example, a subthreshold swing of 11.82 mV/decade and operating voltage of 0.65 V for a drain current of 10⁻⁸ A/µm have been obtained. The physics behind the improved performance is discussed based on the presented model. The analytical model would also be instrumental in designing and optimizing such devices avoiding complexities and cost of numerical models.     

新型槽栅nMOSFET凹槽拐角效应的模拟研究

应用二维器件仿真程序PISCES Ⅱ，模拟计算了新型槽栅结构器件中凹槽拐角效应的影响与作用，讨论了槽栅结构MOSFET的沟道电场特征及其对热载流子效应、阈值电压特性等的影响.槽栅结构的凹槽拐角效应对抑制短沟道效应和抗热载流子效应是十分有利的，并且拐角结构在45°左右时拐角效应最大.调节拐角与其他结构参数，器件的热载流子效应、阈值电压特性、亚阈值特性、输出特性等都会有较大的变化. 关键词： 槽栅MOSFET 拐角效应 阈值电压 热载流子退化     

Electron transport and terahertz radiation detection in submicrometer-sized GaAs/AlGaAs field-effect transistors with two-dimensional electron gas

The electronic transport and response in the terahertz range are studied in field-effect GaAs/AlGaAs transistors with a two-dimensional high-mobility electron gas. The special interest expressed in such transistors stems from the possibility of developing terahertz-range radiation detectors and generators on the basis of these devices. Measurements of the value and the magnetic-field dependence of the drain-source resistance are used to estimate the electron density and mobility in the transistor channel. Results of magnetotransport measurements are employed to interpret the nonresonant detection observed in transistors with a gate width from 0.8 to 2.5 μm. __________ Translated from Fizika Tverdogo Tela, Vol. 46, No. 1, 2004, pp. 146–149. Original Russian Text Copyright ? 2004 by Antonov, Gavrilenko, Demidov, Morozov, Dubinov, Lusakowski, Knap, Dyakonova, Kaminska, Piotrowska, Golaszewska, Shur.     

Measurement of strong photon recycling in ultra‐thin GaAs n/p junctions monolithically integrated in high‐photovoltage vertical epitaxial heterostructure architectures with conversion efficiencies exceeding 60%

Photon‐recycling effects are studied experimentally in photovoltaic power converting III–V semiconductor devices designed with the vertical epitaxial heterostructure architecture (VEHSA). The responsivity of VEHSA structures with multiple thin GaAs n/p junctions is measured for various optical input powers and for different wavelength detuning values with respect to the peak of the spectral response. While the detuning of the optical excitation decreases the external quantum efficiency and the responsivity at low input powers, this study demonstrates that at high optical intensities, a large fraction of the performance can be recovered despite significant detuning values. The photon coupling effects therefore broaden the spectral range for which the VEHSA devices convert high‐power optical inputs with high efficiencies into an electrical output having a preset voltage. The devices exhibit a near optimum responsivity of up to 0.645 A/W for tuned excitation conditions or at high optical intensities for spectral detuning values of up to ～25 nm and corresponding to an external quantum efficiency of ～94%. Efficiencies of 62.0% and 61.8% have been obtained for current‐matched excitations and for a detuning of >10 nm, respectively. An output power of 5.87 W is reported and an open circuit voltage enhancement of 92 meV per n/p junction is measured compared to a device with a side by side planar architecture. (© 2016 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.