Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor(TFET) is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional(2D) models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.     

Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect

A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software.     

新型高速半导体器件IMOS阈值电压解析模型

本文在研究IMOS器件结构的基础上, 分析了该器件不同区域的表面电场, 结合雪崩击穿条件, 建立了P-IMOS的阈值电压解析模型. 应用MATLAB对该器件阈值电压模型与源漏电压、栅长和硅层厚度的关系进行了数值分析, 并用二维器件仿真工具ISE进行了验证. 结果表明, 源电压越大, 阈值电压值越小; 栅长所占比例越大, 阈值电压值越小, 硅层厚度越小, 阈值电压值越小. 本文提出的模型与ISE仿真结果一致, 也与文献报道符合. 这种新型高速半导体器件IMOS阈值电压解析模型的建立为该高性能器件及对应电路的设计、仿真和制造提供了重要的参考.     

Analytical threshold voltage model for strained silicon GAA-TFET

Tunnel field effect transistors(TFETs) are promising devices for low power applications.An analytical threshold voltage model,based on the channel surface potential and electric field obtained by solving the 2D Poisson's equation,for strained silicon gate all around TFETs is proposed.The variation of the threshold voltage with device parameters,such as the strain(Ge mole fraction x),gate oxide thickness,gate oxide permittivity,and channel length has also been investigated.The threshold voltage model is extracted using the peak transconductance method and is verified by good agreement with the results obtained from the TCAD simulation.     

Quasi-two-dimensional threshold voltage model for junctionless cylindrical surrounding gate metal-oxide-semiconductor field-effect transistor with dual-material gate

Based on the quasi-two-dimensional(2D) solution of Poisson’s equation in two continuous channel regions, an analytical threshold voltage model for short-channel junctionless dual-material cylindrical surrounding-gate(JLDMCSG) metal-oxide-semiconductor field-effect transistor(MOSFET) is developed. Using the derived model, channel potential distribution, horizontal electrical field distribution, and threshold voltage roll-off of JLDMCSG MOSFET are investigated. Compared with junctionless single-material CSG(JLSGCSG) MOSFET, JLDMCSG MOSFET can effectively suppress short-channel effects and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage rolloff of JLDMCSG can be significantly reduced by adopting both a small oxide thickness and a small silicon channel radius. The model is verified by comparing its calculated results with that obtained from three-dimensional(3D) numerical device simulator ISE.     

亚100 nm应变Si/SiGe nMOSFET阈值电压二维解析模型

本文基于二维泊松方程,建立了适用于亚100 nm应变Si/SiGe nMOSFET的阈值电压理论模型.为了保证该模型的准确性,同时考虑了器件尺寸减小所导致的物理效应,如短沟道效应,量子化效应等.通过将模型的计算结果与二维器件模拟器ISE的仿真结果进行对比分析,证明了本文提出的模型的正确性.最后,还讨论了亚100 nm器件中常规工艺对阈值电压的影响.该模型为亚100 nm小尺寸应变Si器件的分析设计提供了一定的参考. 关键词： 亚100nm 应变Si/SiGe nMOSFET 二维表面势 阈值电压     

单轴应变SiNMOSFET源漏电流特性模型

本文在建立单轴应变Si NMOSFET迁移率模型和阈值电压模型的基础上, 基于器件不同的工作区域, 从基本的漂移扩散方程出发, 分别建立了单轴应变Si NMOSFET源漏电流模型. 其中将应力的影响显式地体现在迁移率和阈值电压模型中, 使得所建立的模型能直观地反映出源漏电流特性与应力强度的关系. 并且对于亚阈区电流模型, 基于亚阈区反型电荷, 而不是采用常用的有效沟道厚度近似的概念, 从而提高了模型的精度. 同时将所建模型的仿真结果与实验结果进行了比较, 验证了模型的可行性. 该模型已经被嵌入进电路仿真器中, 实现了对单轴应变Si MOSFET 器件和电路的模拟仿真.     

异质栅全耗尽应变硅金属氧化物半导体模型化研究

为了进一步提高小尺寸金属氧化物半导体(MOSFET)的性能,在应变硅器件的基础上, 提出了一种新型的异质栅MOSFET器件结构.通过求解二维Poisson方程,结合应变硅技术的物理原理,建立了表面势、表面电场以及阈值电压的物理模型,研究了栅金属长度、功函数以及双轴应变对其的影响. 通过仿真软件ISE TCAD进行模拟仿真,模型计算与数值模拟的结果基本符合. 研究表明：与传统器件相比,本文提出的异质栅应变硅新器件结构的载流子输运效率进一步提高, 可以很好地抑制小尺寸器件的短沟道效应、漏极感应势垒降低效应和热载流子效应, 使器件性能得到了很大的提升. 关键词： 应变硅 异质栅 阈值电压 解析模型     

Extended-source broken gate tunnel FET for improving direct current and analog/radio-frequency performance

The various advantages of extended-source(ES), broken gate(BG), and hetero-gate-dielectric(HGD) technology are blended together for the proposed tunnel field-effect transistor(ESBG TFET) in order to enhance the direct-current and analog/radio-frequency performance. The source of the ESBG TFET is extended into channel for the purpose of increasing the point and line tunneling in the device at the tunneling junction, and then, the on-state current for the ESBG TFET increases. The influence of the source region length on the direct-current and radio-frequency performance parameters of the ESBG TFET is analyzed in detail. The results show that the proposed TFET exhibits a high on-state current to off-state current ratio of 1013, large transconductance of 1200 μS/μm, high cut-off frequency of 72.8 GHz, and high gain bandwidth product of 14.3 GHz. Apart from these parameters, the ESBG TFET also demonstrates high linearity distortion parameters in terms of the second-and third-order voltage intercept points, the third-order input interception point, and the third-order intermodulation distortion. Therefore, the ESBG TFET greatly promotes the application potential of conventional TFETs.     

A threshold voltage model of short-channel fully-depleted recessed-source/drain(Re-S/D) SOI MOSFETs with high-k dielectric

In this paper, a surface potential based threshold voltage model of fully-depleted(FD) recessed-source/drain(Re-S/D)silicon-on-insulator(SOI) metal-oxide semiconductor field-effect transistor(MOSFET) is presented while considering the effects of high-k gate-dielectric material induced fringing-field. The two-dimensional(2D) Poisson's equation is solved in a channel region in order to obtain the surface potential under the assumption of the parabolic potential profile in the transverse direction of the channel with appropriate boundary conditions. The accuracy of the model is verified by comparing the model's results with the 2D simulation results from ATLAS over a wide range of channel lengths and other parameters,including the dielectric constant of gate-dielectric material.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO₂ /Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor(MOSFET) are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson’s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson’s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.     

对称三材料双栅应变硅金属氧化物半导体场效应晶体管二维解析模型

提出了对称三材料双栅应变硅金属氧化物半导体场效应晶体管器件结构,为该器件结构建立了全耗尽条件下的表面势模型、表面场强和阈值电压解析模型,并分析了应变对表面势、表面场强和阈值电压的影响,讨论了三栅长度比率对阈值电压和漏致势垒降低效应的影响,对该结构器件与单材料双栅结构器件的性能进行了对比研究.结果表明,该结构能进一步提高载流子的输运速率,更好地抑制漏致势垒降低效应.适当优化三材料栅的栅长比率,可以增强器件对短沟道效应和漏致势垒降低效应的抑制能力.     

A two-dimensional analytical modeling for channel potential and threshold voltage of short channel triple material symmetrical gate Stack(TMGS) DG-MOSFET

In the present work, a two-dimensional(2D) analytical framework of triple material symmetrical gate stack(TMGS)DG-MOSFET is presented in order to subdue the short channel effects. A lightly doped channel along with triple material gate having different work functions and symmetrical gate stack structure, showcases substantial betterment in quashing short channel effects to a good extent. The device functioning amends in terms of improved exemption to threshold voltage roll-off, thereby suppressing the short channel effects. The encroachments of respective device arguments on the threshold voltage of the proposed structure are examined in detail. The significant outcomes are compared with the numerical simulation data obtained by using 2D ATLAS~(TM) device simulator to affirm and formalize the proposed device structure.     

Optimization of two-dimensional electron gases and – characteristics for AlGaN/GaN HEMT devices

In this paper, we take account of the spontaneous and piezoelectric polarization effect at the heterointerface in the AlGaN/GaN HEMT device, and one-dimensional Schrödinger–Poisson equations are solved self-consistently using a nonuniform mesh; using our findings, the AlGaN/GaN heterostructure conduction band and the two-dimensional electron gas (2DEG) density are investigated. The dependences of the 2DEG characteristics on the Al fraction, the thickness of each layer, the donor concentration and the gate voltage are investigated through simulation. The output characteristics are simulated using a quasi-2D model; a saturation voltage and threshold voltage are also shown. The influence of the spacer layer width on the 2DEG density is calculated for the first time. An explanation and analyses are given.     

3-D numerical modeling and simulation of nanoscale FinFET for the application in ULSI circuits

A complete three-dimensional numerical modeling of nanoscale FinFET including quantum-mechanical effects for the application in future ULSI circuits has been developed. The exact potential profile in the channel has been computed by obtaining a self-consistent solution of 3D Poisson–Schrödinger equation using Leibmann's iteration method. The threshold voltage shift, drain and transfer characteristics have been estimated and the results were compared with the device simulator and experimental results. The model is purely a physics based one and overcomes the major limitations of the existing 2D/3D analytical models by providing a more accurate result and this model is validated by comparing with the existing results as well as the experimental results.     

小尺寸应变Si nMOSFET物理模型的研究

本文运用高斯定律得出多晶SiGe栅应变Si nMOSFET的准二维阈值电压模型,并从电流密度方程出发建立了小尺寸应变Si nMOS器件的I-V特性模型.对所得模型进行计算分析,得出沟道Ge组分、多晶Si_1-yGe_y栅Ge组分、栅氧化层厚度、应变Si层厚度、栅长以及掺杂浓度对阈值电压的影响.运用二维器件模拟器对器件表面势和I-V特性进行了仿真,所得结果与模型仿真结果一致,从而证明了模型的正确性. 关键词： 多晶SiGe栅 高斯定理 阈值电压 速度过冲     

An analytical model for nanowire junctionless SOI Fin FETs with considering three-dimensional coupling effect

In this paper, the three-dimensional(3D) coupling effect is discussed for nanowire junctionless silicon-on-insulator(SOI) Fin FETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional(2D) potential model is proposed for the subthreshold region of junctionless SOI Fin FET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.     

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance

An analytical model for a novel triple reduced surface field(RESURF) silicon-on-insulator(SOI) lateral doublediffused metal–oxide–semiconductor(LDMOS) field effect transistor with n-type top(N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional(2D) Poisson's equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage(BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer(Q_(ntop)) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.     

Effect of gate engineering in JLSRG MOSFET to suppress SCEs: An analytical study

In this work, an analytical model of gate-engineered junctionless surrounding gate MOSFET (JLSRG) has been proposed to uncover its potential benefit to suppress short-channel effects (SCEs). Analytical modelling of centre potential for gate-engineered JLSRG devices has been developed using parabolic approximation method. From the developed centre potential, the parameters like threshold voltage, surface potential, Electric Field, Drain-induced Barrier Lowering (DIBL) and subthershold swing are determined. A nice agreement between the results obtained from the model and TCAD simulation demonstrates the validity and correctness of the model. A comparative study of the efficacy to suppress SCEs for Dual-Material (DM) and Single-Material (SM) junctionless surrounding gate MOSFET of the same dimensions has also been carried out. Result indicates that TM-JLSRG devices offer a noticeable enhancement in the efficacy to suppress SCEs by as compared to SM-JLSRG and DM-JLSRG device structures. The effect of different length ratios of three channel regions related to three different gate materials of TM-JLSRG structure on the SCEs have also been discussed. As a result, we demonstrate that TM-JLSRG device can be considered as a competitive contender to the deep-submicron mainstream MOSFETs for low-power VLSI applications.     

A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs

In this paper the influences of the metal-gate and high-k/SiO 2 /Si stacked structure on the metal-oxide-semiconductor field-effect transistor（MOSFET） are investigated.The flat-band voltage is revised by considering the influences of stacked structure and metal-semiconductor work function fluctuation.The two-dimensional Poisson＇s equation of potential distribution is presented.A threshold voltage analytical model for metal-gate/high-k/SiO 2 /Si stacked MOSFETs is developed by solving these Poisson＇s equations using the boundary conditions.The model is verified by a two-dimensional device simulator,which provides the basic design guidance for metal-gate/high-k/SiO 2 /Si stacked MOSFETs.