低功耗限制的级间匹配型2.45GHz低噪声放大器设计

文章在分析传统LNA结构的基础上,针对其存在的两个问题,提出了相应的改进方法,并用chartered0.35umRFCMOS工艺设计了一个工作于2.45GHz的LNA.改进之一是在共源共栅管之间加一匹配电感,抑制共栅管对噪声系数的影响,使噪声系数从1.759dB降低为1.63dB,增益从32.36dB增大到36_31dB.之二是在输入管的栅源之间加一电容,保证了在功耗降低的情况下,仍然能同时满足功率和噪声匹配要求,使噪声系数基本保持不变.     

0.5～3.3GHz超宽带低噪声放大器设计

选用Agilent公司的PHEMT晶体管ATF-54143,基于负反馈技术,设计了一种超宽带低噪声放大器.其匹配网络是由微带与集总元件共同组成,使用ADS2009对整个电路进行优化设计.在0.5～3.3 GHz的超宽带频率范围内,低噪声放大器增益大于25 dB,增益不平坦度为1.5,噪声系数不大于2 dB.可用相对介电常数为9.2、厚度为1 mm的介质基板实现该放大器,可应用于各种微波通信领域.     

基于自适应遗传算法的低噪声放大器设计

低噪声放大器是射频接收系统的关键组成部分,决定了系统的噪声特性,直接影响接收灵敏度。提出一种利用自适应遗传算法设计低噪声放大器匹配电路的思路,自动优化交叉概率和变异概率,避免了易早熟的缺点。采用这一算法进行了放大器设计实验,放大器具有较低的噪声系数、较高的放大增益,以及较好的带外抑制效果。实验结果表明实测和软件仿真性能吻合较好,证明了自适应遗传算法设计的可靠性。     

基于0.13-µm SiGe BiCMOS工艺的40GHz低噪声放大器设计

设计了一个工作于40 GHz的低噪声放大器,提出了一种改进的Cascode电路结构并设计了匹配网络。为了获取高Q值,电感使用了共面波导短路线实现。电路使用0.13-µm SiGe BiCMOS工艺,其截止频率fT 为103GHz,芯片尺寸为0.21 mm2。该低噪声放大器使用一级Cascode电路结构,-3dB带宽为34GHz到44GHz.。在40GHz频率点上,测量的增益为8.6dB,输入回波损耗S11为-16.2dB。仿真的噪声系数为5dB。在2.5V供电电压下,电路消耗的电流仅为3mA。     

一种低功耗2.4GHz低噪声放大器设计

设计了一个低功耗2.4 GHz低噪声放大器,并详细阐述了电路的噪声匹配理论.该低噪声放大器采用经典的共源共栅结构,为了同时满足共轭匹配与噪声匹配,在输入管的栅源间增加了一个电容Cex.电路设计采用SMIC 65 nm CMOS工艺,并用Cadence进行仿真.仿真结果表明:电路在1.2V电源电压下的功耗小于7 mW,噪...     

声频放大器低噪声化的设计

本文首先从低噪声放大器设计的基本原理和方法入手，对晶体管放大器的噪声模型（Ｅｎ－Ｉｎ模型）做了分析，并以实现放大器低噪声化为出发点，阐述了具体设计的几个过程，最后对级联放大器的低噪声设计进行探讨。本文并非从工程设计的角度全面论述低噪声设计的各个方面，而是仅就低噪声设计中需要考虑的一些问题做一概述，从而为一些有志于音响工作的人们研究低噪声系统的设计问题提供方便。     

一种1.5GHz0.25μmCMOS低噪声放大器设计

提出并设计了一种应用于GPS接收机中的1.5 GHz低噪声放大器,该放大器采用TSMC 0.25μm RF CMOS工艺制作.与传统的共源共栅结构相比,该电路引入了级间耦合电容,使整个电路的功率增益、噪声系数等关键性能指标得到改善.该放大器的正向功率增益为21.8 dB,NF为0.96 dB,IIP3为-11 dBm,功耗为20 mW,且输入输出阻抗匹配良好,满足GPS接收机射频前端对低噪声放大器的要求.     

射频CMOS低噪声放大器输入匹配网络的研究与设计

本文对低功耗射频CMOS低噪声放大器的输入匹配网络进行了研究。采用台积电TSMC0.18μmCMOS工艺模型,通过ADS电路仿真软件对设计的低噪声放大器电路进行了优化设计和仿真,仿真结果表明在2.4GHz中心工作频率下,该低噪声放大器满足射频接收机的系统要求,它的噪声系数NF约为2.57dB,增益S21约为16.2dB,输入反射系数S11约为-13.3dB,输出反射系数S22约为-21.9dB。电路的输入匹配和输出匹配情况良好。     

2.4 GHz高增益极低噪声放大器设计

基于ADS仿真技术,提出了微带线代替电感的负反馈方式,保证电路稳定性的同时,采用微带线代替电感、电容实现放大器的匹配,方便调试并节省了成本。经过优化与调试,最终设计了一种2.4 GHz频段极低噪声高增益的低噪声放大器。实测结果与仿真结果保持一致,在2.4 GHz~2.5 GHz范围内,驻波比VSWR≤1.45,增益GAIN≥12 d B,噪声系数NF≤0.63。高增益极低噪声放大器用于WLAN系统,能提高通信距离和通信容量,改善通信质量。     

运用级间并联电感的级联CMOS低噪声放大器的优化设计

本文介绍了一种运用级间并联电感优化CMOS低噪声放大器的设计方法。传统的级联低噪声放大器可以从两级级联放大器的角度出发,视为共源级和共栅级的级联,由于共栅极的极好的隔离性,两级放大器可以分别设计。理论分析表明：在共源极和共栅极间引入级间匹配网络,即并联一个电感加强两极间的耦合,可以有效的改善低噪放的功率增益和噪声性能。文章最后用一个工作于5GHz的低噪放的设计实例,验证了理论分析的正确性。     

A CMOS low noise amplifier with integrated front-side micromachined inductor

The paper presents the design and characterization of a low noise amplifier (LNA) in a 0.18 μm CMOS process with a novel micromachined integrated stacked inductor. The inductor is released from the silicon substrate by a low-cost CMOS compatible dry front-side micromachining process that enables higher inductor quality factor and self-resonance frequency. The post-processed micromachined inductor is used in the matching network of a single stage cascode 4 GHz LNA to improve its RF performance. This study compares performance of the fabricated LNA prior to and after post-processing of the inductor. The measurement results show a 0.5 dB improvement in the minimum noise figure and a 1 dB increase in gain, while good input matching is maintained. These results show that the novel low-cost CMOS compatible front-side dry micromachining process reported here significantly improves performance and is very promising for System-On-Chip (SOC) applications.     

Design of on-chip 15-18 GHz ultra low noise amplifier

With rapid development communication system, high signal to noise ratio （SNR） system is required. In high frequency bandwidth, high loss, low Q inductors and high noise figure is a significant challenge with on-chip monolithic microwave integrated circuits （MMICs）. To overcome this problem, high Q, low loss transmission line characteristics was analyzed. Compared with the same inductor value of the lumped component and the transmission line, it has a higher Q value and lower loss performance in high frequency, and a 2-stage common-source low noise amplifier （LNA） was presented, which employs source inductor feedback technology and high Q low loss transmission line matching network technique with over 17.6 dB small signal gain and 1.1 dB noise figure in 15 GHz-18 GHz. The LNA was fabricated by WIN semiconductors company 0.15 μm gallium arsenide （GaAs） P high electron mobility transistor （P-HEMT） process. The total Current is 15 mA, while the DC power consumption is only 45 mW.     

A 1.5-V, 1.5-GHz CMOS low noise amplifier

A 1.5-GHz low noise amplifier (LNA), intended for use in a global positioning system (GPS) receiver, has been implemented in a standard 0.6-μm CMOS process. The amplifier provides a forward gain (S21) of 22 dB with a noise figure of only 3.5 dB while drawing 30 mW from a 1.5 V supply. In this paper, we present a detailed analysis of the LNA architecture, including a discussion on the effects of induced gate noise in MOS devices     

CMOS planar spiral inductor modeling and low noise amplifier design

During this study, various narrowband single-ended inductive source degenerated Low Noise Amplifiers (LNAs) for GSM and S-band low earth orbit (LEO) space applications have been designed, simulated and compared using Mietec CMOS 0.7 μm process and the Cadence/BSIM3v3. To get more realistic results, parasitic effects due to layout have been calculated and added to the simulations. Also, considering the inductive source degenerative topology, most of the attention is given on the modeling of planar spiral inductor by lumped element circuits. Moreover to decrease the substrate effects, the inductors have been surrounded by grounded guard rings and have patterned ground shield (PGS) under them. The simulation results of LNA including the parasitic effects indicate a forward gain of 9 dB with noise figure of 4.5 dB while drawing 18 mW from+3 V supply at 2210 MHz. The area occupied is 1.8 mm×1.6 mm with pads, 1.3 mm×1.2 mm without pads.     

26-42 GHz SOI CMOS low noise amplifier

A complementary metal-oxide semiconductor (CMOS) single-stage cascode low-noise amplifier (LNA) is presented in this paper. The microwave monolithic integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator (SOI) technology. All impedance matching and bias elements are implemented on the compact chip, which has a size of 0.6 mm /spl times/ 0.3 mm. The supply voltage and supply current are 2.4 V and 17 mA, respectively. At 35 GHz and 50 /spl Omega/ source/load impedances, a gain of 11.9 dB, a noise figure of 3.6 dB, an output compression point of 4 dBm, an input return loss of 6 dB, and an output return loss of 18 dB are measured. The -3-dB frequency bandwidth ranges from 26 to 42 GHz. All results include the pad parasitics. To the knowledge of the author, the results are by far the best for a silicon-based millimeter-wave LNA reported to date. The LNA is well suited for systems operating in accordance to the local multipoint distribution service (LMDS) standards at 28 and 38 GHz and the multipoint video distribution system (MVDS) standard at 42 GHz.     

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.     

60 GHz compact low noise amplifier in 65 nm CMOS

A single-ended low noise amplifier in 65 nm CMOS for applications at 60 GHz is presented. Its measured gain and noise figure at the centre frequency of 57 GHz are 19.1 dB and 5.5 dB, respectively, and it provides wideband matching. Transistors in the design have an asymmetrically fingered layout which reduces parasitic capacitances while simultaneously allowing for higher channel current densities.     

低噪声放大器的设计与仿真

论述了在射频电路仿真软件ADS中实现低噪声放大器的整个设计过程,包括低噪声放大器的晶体管的选取、输入输出匹配网络设计以及实现形式等.结合版图与系统结构框图,论述该设计的微调小岛与扇形开路支节等结构应用,同时指出结构尺寸设计的理论依据.最终以图形方式给出满足指标要求的设计结果.