结终端采用JTE保护技术的4H-SiC PiN二极管模拟和研制

利用二维器件模拟软件ISE-TCAD 10.0,对结终端采用结扩展保护技术的4H-SiC PiN二极管平面器件进行反向耐压特性的模拟,并获得许多有价值的模拟数据.依据所得的模拟数据进行此种二极管器件的研制.实验测试表明,此二极管的模拟优化数据与实验测试的结果一致性较好,4H-SiC PiN二极管所测得到的反向电压达1600 V,该反向耐压数值达到理想平面结的击穿耐压90%以上.     

电荷直接隧穿特征时间的计算模型

在分析硅基纳米存储器的势结构和价带混合效应对直接隧穿过程影响的基础上,采用顺序隧穿理论和巴丁传输哈密顿方法,发展了电子和空穴直接隧穿时间的计算模型.利用该模型数值计算了硅基纳米存储器的编程时间和保留时间,讨论了结构参数和外加偏压对器件存储性能的影响,指出需要设计新的器件结构模型来优化硅基纳米存储器的保留特性.     

套刻偏差对4H-SiC 浮动结结势垒肖特基二极管的影响研究

4H-SiC浮动结结势垒肖特基二极管与常规结势垒肖特基二极管相比在 相同的导通电阻条件下具有更高的击穿电压. 由p⁺埋层形成的浮动结与主结p⁺区 之间的套刻对准是实现该结构的一项关键技术. 二维模拟软件ISE的模拟结果表明, 套刻偏差的存在会明显影响器件的击穿特性, 随着偏差的增大击穿电压减小. 尽管主结和埋层的交错结构与对准结构具有相似的击穿特性, 但是当正向电压大于2 V后, 交错结构的串联电阻更大.     

势垒可调的氧化镓肖特基二极管

氧化镓作为新一代宽禁带材料,其器件具有优越的性能.本文仿真研究了n~+高浓度外延薄层对氧化镓肖特基二极管的势垒调控.模拟结果显示,当n型氧化镓外延厚度为5 nm、掺杂浓度为2.6×10¹⁸ cm^-3时,肖特基二极管纵向电流密度高达496.88 A/cm~2、反向击穿电压为182.30 V、导通电阻为0.27 mΩ·cm~2,品质因子可达123.09 MW/cm~2.进一步研究发现肖特基二极管的性能与n~+外延层厚度和浓度有关,其电流密度随n~+外延层的厚度和浓度的增大而增大.分析表明,n~+外延层对势垒的调控在于镜像力、串联电阻及隧穿效应综合影响,其中镜像力和串联电阻对势垒的降低作用较小,而高电场下隧穿效应变得十分显著,使得热发射电流增大的同时,隧穿电流得到大幅度提升,从而进一步提升了氧化镓肖特基二极管的性能.     

半导体量子器件物理讲座第四讲 共振隧穿器件及其电路应用

当一个电子的能量低于势垒高度时,它仍可以隧穿通过势垒,在一定条件下,双势垒结构中电子的隧穿几率甚至可以接近1,利用这种共振隧穿现象可以做成共振隧穿二极管,它的电流－电压特性曲线中会出现负微分电阻,利用这种负阻效应可以做成高频振荡器和倍频器等电子器件,双势垒结构与通常的双极晶体管结合可以做成共振隧穿双极晶体管,它们可以用来做成多态记忆器和模数转换器等器件。     

电压应力下超薄栅氧化层n-MOSFET的击穿特性

研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性，包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性，分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透.在电压应力下，SiO₂中形成的缺陷不仅降低了SiO₂的势垒高度，而且等效减小了SiO₂的厚度(势垒宽度).另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长. 关键词： 超薄栅氧化层 斜坡电压 经时击穿 渗透     

基于多物理场计算的二极管雪崩击穿效应分析

基于电磁场、半导体物理及热力学方程的半导体器件多物理场模型方程组共同描述了器件内部的电热特性。而半导体器件在反向电压作用下,会发生碰撞电离及雪崩击穿现象。采用多物理场计算方法仿真型号为HSMS-282C的肖特基二极管的雪崩击穿现象,仿真结果与实验测量结果吻合,表明该算法能准确表征二极管物理特性,并对效应现象给出物理机理解释。     

Ni/4H-SiC肖特基势垒二极管的γ射线辐照效应

对制备的Ni/4H-SiC肖特基势垒二极管（SBD）进行了γ射线辐照试验,并在辐照过程中对器件分别加0和-30?V偏压.经过1?Mrad（Si）总剂量的γ射线辐照后,不同辐照偏压下的Ni/4H-SiC肖特基接触的势垒高度和理想因子没有退化,SiC外延层中的少子寿命也没有退化.辐照后器件的反向电流下降,这是由于器件表面的负界面电荷增加引起的.研究表明,辐照偏压对Ni/4H-SiC SBD的辐照退化效应没有明显的影响. 关键词： 碳化硅 肖特基 辐照效应 偏压     

单轴应变硅nMOSFET栅隧穿电流模型

本文基于量子机制建立了单轴应变硅nMOSFET栅隧穿电流模型,分析了隧穿电流与器件结构参数、偏置电压及应力的关系.仿真分析结果与单轴应变硅nMOSFET的实验结果符合较好,表明该模型可行.同时与具有相同条件的双轴应变硅nMOSFET的实验结果相比,隧穿电流更小,从而表明单轴应变硅器件更具有优势.该模型物理机理明确,不仅适用于单轴应变硅nMOSFET,只要将相关的参数置换,该模型也同样适用于单轴应变硅pMOSFETs. 关键词： 单轴应变 nMOSFET 栅隧穿电流 模型     

新型量子器件—共振隧穿二极管和三极管的原理及应用前景

量子器件是近年来电子器件研制的一个前沿领域．本文从电子共振隧穿双势垒的基本概念出发，介绍在此基础上发展起来的一类重要的量子器件，即量子共振隧穿二极管和三极管的基本原理．现在巳有可在室温下工作的这类器件原型，本文以两个具体的实例说明这类新型量子器件作为功能性器件的巨大潜力．     

Numerical modelling of anisotropy in 4H－SiC MESFET‘s

A numerical model for 4H-SiC MESFET anisotropy is presented in this paper and the device performances, such as breakdown, temperature and transient characteristics, are demonstrated. The simulation results show obvious effects of the anisotropy for 4H-SiC and are in better accordance with the experimental results. The anisotropy for 4H-SiC should be involved in the device design to acquire better performances.     

Fabrication of ZnO nanorod-based p–n heterojunction on SiC substrate

Due to the special properties of ZnO and numerous envisaged areas of application of its nanostructures, much effort has been made in fabricating ZnO nanostructures. The next challenging step seems to be the processing and hence realisation of devices based on the nanostructure. We have grown ZnO nanorods of high crystal quality and good optical properties on 6H-SiC and 4H-SiC substrates. Considering the p–n junction as a basis for electronic and optoelectronic devices, we realised ohmic contacts on p-type 4H-SiC and fabricated ZnO nanorod-based p–n heterojunctions with the p-type 4H-SiC serving as the hole-conducting region. Nanorod-based p–n diodes with a turn-on voltage of 1.8 V and relatively large reverse-bias breakdown voltage were obtained, thus suggesting both the possibility of ZnO nanorod-based ultraviolet photodetectors and light-emitting devices, and the miniaturisation of device scales.     

Investigation of the 4H-SiC surface

The silicon carbide (SiC) surface is more complex than that of silicon and can be carbon-terminated or silicon-terminated, and can exist as several reconstructions. Investigations of the surface structure as a function of temperature, under ultrahigh vacuum (UHV) conditions using scanning tunneling microscopy (STM) and low energy electron diffraction (LEED), are presented. The 4H-SiC surface can be passivated using a silicon deposition/evaporation technique to reconstruct the surface. This has a significant effect on the electrical behaviour of metal contacts to the silicon carbide surface, critical in any electronic device. Atomic resolution STM studies of the 4H-SiC surface have revealed step features and micropipe defects in unprecedented detail. STM has also been used to image clusters of metal deposited on the 4H-SiC surface. The effect of annealing on the behaviour of these nickel clusters is also presented. The surface of the silicon carbide is extremely important in the fabrication of silicon carbide electronic devices and this paper presents a discussion of the SiC surface with particular reference to its impact on SiC device applications in power electronics.     

A simplified post-soft-breakdown current model for MOS devices

Based on the tunneling current model, a simplified current model is developed for MOS devices after soft breakdown (SBD). The post-soft-breakdown current consists of modified direct tunneling current and Fowler Nordheim (FN) tunneling current. Considering the change of gate oxide after soft breakdown, impacts of soft breakdown on the dielectric constant, and effective electron mass of the gate oxide are discussed, and their values are obtained by fitting simulation results to experimental data. It is found that the effective electron mass is decreased after soft breakdown due to damaged oxide, while the dielectric constant is increased after soft breakdown due to interface distortion. In this way, the leakage current after soft breakdown can be accurately calculated. The validity of the proposed model is confirmed by experimental results. Z.L. Li currently is with the Department of Electrical and Electronic Engineering, University of Hong Kong.     

The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al₂O₃ as the gate dielectric, deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8⁰N-/N+ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al₂O₃ gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties (1×10¹⁴ cm^-2) and low gate-leakage current (I_G = 1 × 10^-3 A/cm^-2@E_ox = 8 MV/cm). Analysis of the current conduction mechanism on the deposited Al₂O₃ gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al₂O₃ is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.     

Fabrications and characterizations of high performance 1.2 kV,3.3 kV,and 5.0 kV class 4H–SiC power SBDs

In this paper, 1.2 kV, 3.3 kV, and 5.0 kV class 4H–SiC power Schottky barrier diodes(SBDs)are fabricated with three N-type drift layer thickness values of 10 μm, 30 μm, and 50 μm, respectively. The avalanche breakdown capabilities,static and transient characteristics of the fabricated devices are measured in detail and compared with the theoretical predictions. It is found that the experimental results match well with the theoretical calculation results and are very close to the 4H–SiC theoretical limit line. The best achieved breakdown voltages(BVs) of the diodes on the 10 μm, 30 μm, and 50 μm epilayers are 1400 V, 3320 V, and 5200 V, respectively. Differential specific-on resistances(R_(on-sp)) are 2.1 m?·cm~2,7.34m?·cm~2, and 30.3 m?·cm~2, respectively.     

Fabrication and characteristics of lateral Ti/4H-SiC Schottky barrier diodes

This paper describes the fabrication and characteristics of the lateral Ti/4H-SiC Schottky barrier diodes (SBDs). SBDs are fabricated by nitrogen ion implantation into p-type 4H-SiC epitaxial layer. The implant depth profile is simulated using the Monte Carlo simulator TRIM. Measurements of the reverse I－V characteristics demonstrate a low reverse current, that is good enough for many SiC-based devices such as SiC metal-semiconductor field-effect transistors, and SiC static induction transistors. The parameters of the diodes are extracted from the forward I－V characteristics. The barrier height φ_b of Ti/4H-SiC is 0.95 eV.     

电荷失配对SiC半超结垂直双扩散金属氧化物半导体场效应管击穿电压的影响

Si C半超结垂直双扩散金属氧化物半导体场效应管(VDMOSFET)相对于常规VDMOSFET在相同导通电阻下具有更大击穿电压.在N型外延层上进行离子注入形成半超结结构中的P柱是制造Si C半超结VDMOSFET的关键工艺.本文通过二维数值仿真研究了离子注入导致的电荷失配对4H-Si C超结和半超结VDMOSFET击穿电压的影响,在电荷失配程度为30%时出现半超结VDMOSFET的最大击穿电压.在本文的器件参数下,P柱浓度偏差导致击穿电压降低15%时,半超结VDMOSFET柱区浓度偏差范围相对于超结VDMOSFET可提高69.5%,这意味着半超结VDMOSFET对柱区离子注入的控制要求更低,工艺制造难度更低.     

Low frequency effects of surface states on 4H—SiC metal—semiconductor field effect transistor

The process-related surface state effect is investigated the fabrication of SiC devices, and a nonllnear model for 4H-SiC power metal-semiconductor field effect transistor (MESFET) is propose, which takes into account the surface related parameters. The frequency-and temperature-dependent transconductance dispersion is readily demonstrated in terms of the improved model. Simulation results show that larger dispersion and higher transition frequency occur in 4H-SiC MESFET than in GaAs MESFET. The advantage of this analytical model over the two-dimensional numerical simulation is the simplicity of calculations, therefore it is suitable for the processing improvement of SiC devices