Double step buried oxide (DSBO) SOI-MOSFET: A proposed structure for improving self-heating effects

For the first time, a novel structure named as double step buried oxide silicon-on-insulator-MOSFET (DSBO-SOI) is proposed, which can combine the advantages of both SOI structure and bulk structure. Design consideration for a 30 nm channel length SOI-MOSFET employing double step buried oxide (DSBO) is presented. The electrical characteristics and temperature distribution are analyzed and compared with ultra-thin body silicon-on-insulator (UTB-SOI) MOSFET. The DSBO devices are shown to have better leakage and sub-threshold characteristics. Furthermore, the channel temperature is reduced during high-temperature operation and drain current increase suggesting that DSBO can mitigate the self-heating penalty effectively. Our results suggest that DSBO is an alternative to silicon dioxide as the buried dielectric in SOI, and expands the application of SOI to high temperature.     

超短沟道绝缘层上硅平面场效应晶体管中热载流子注入应力导致的退化对沟道长度的依赖性

随着场效应晶体管(MOSFET)器件尺寸的进一步缩小和器件新结构的引入, 学术界和工业界对器件中热载流子注入(hot carrier injections, HCI)所引起的可靠性问题日益关注. 本文研究了超短沟道长度(L=30–150 nm)绝缘层上硅(silicon on insulator, SOI)场效应晶体管在HCI应力下的电学性能退化机理. 研究结果表明, 在超短沟道情况下, HCI 应力导致的退化随着沟道长度变小而减轻. 通过研究不同栅长器件的恢复特性可以看出, 该现象是由于随着沟道长度的减小, HCI应力下偏压温度不稳定性效应所占比例变大而导致的. 此外, 本文关于SOI器件中HCI应力导致的退化和器件栅长关系的结果与最近报道的鳍式场效晶体管(FinFET)中的结果相反. 因此, 在超短沟道情况下, SOI平面MOSFET器件有可能具有比FinFET器件更好的HCI可靠性.     

高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响

研究了高k栅介质对肖特基源漏超薄体SOI MOSFET性能的影响.随着栅介质介电常数增大,肖特基源漏(SBSD) SOI MOSFET的开态电流减小,这表明边缘感应势垒降低效应(FIBL)并不是对势垒产生影响的主要机理.源端附近边缘感应势垒屏蔽效应(FIBS)是SBSD SOI MOSFET开态电流减小的主要原因.同时还发现,源漏与栅是否对准,高k栅介质对器件性能的影响也不相同.如果源漏与栅交叠,高k栅介质与硅衬底之间加入过渡层可以有效地抑制FIBS效应.如果源漏偏离栅,采用高k侧墙并结合堆叠栅结构,可以提高驱动电流.分析结果表明,来自栅极的电力线在介电常数不同的材料界面发生两次折射.根据结构参数的不同可以调节电力线的疏密,从而达到改变势垒高度,调节驱动电流的目的. 关键词： k栅介质')" href="#">高k栅介质 肖特基源漏(SBSD) 边缘感应势垒屏蔽(FIBS) 绝缘衬底上的硅(SOI)     

非对称Halo异质栅应变Si SOI MOSFET的二维解析模型

为了进一步提高深亚微米SOI (Silicon-On-Insulator) MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) 的电流驱动能力, 抑制短沟道效应和漏致势垒降低效应, 提出了非对称Halo异质栅应变Si SOI MOSFET. 在沟道源端一侧引入高掺杂Halo结构, 栅极由不同功函数的两种材料组成. 考虑新器件结构特点和应变的影响, 修正了平带电压和内建电势. 为新结构器件建立了全耗尽条件下的表面势和阈值电压二维解析模型. 模型详细分析了应变对表面势、表面场强、阈值电压的影响, 考虑了金属栅长度及功函数差变化的影响. 研究结果表明,提出的新器件结构能进一步提高电流驱动能力, 抑制短沟道效应和抑制漏致势垒降低效应, 为新器件物理参数设计提供了重要参考. 关键词： 非对称Halo 异质栅 应变Si 短沟道效应     

MOSFET scaling into the 10 nm regime

Scaling limits of the double-gate MOSFET structure are explored. Because short-channel effects can be adequately controlled by thinning the silicon body, the eventual scaling limit will be determined by the ability to control off-state leakage due to quantum mechanical tunneling and thermionic emission between the source and drain. Depending on threshold voltage and the source/drain doping profile, this will restrict gate length scaling to 5–11 nm. As power supplies are scaled down, maintaining on-state drive current may become difficult due to threshold voltage limitations. Series resistance becomes important as the body thickness is reduced, but intrinsic device performance may still be improved.     

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain(LDD) region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson’s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.     

Novel attributes of AlGaN/AlN/GaN/SiC HEMTs with the multiple indented channel

In this paper, a high performance AlGaN/AlN/GaN/SiC High Electron Mobility Transistor (HEMT) with the multiple indented channel (MIC-HEMT) is proposed. The main focus of the proposed structure is based on reduction of the space around the gate, stop of the spread of the depletion region around the source–drain, and decrement of the thickness of the channel between the gate and drain. Therefore, the breakdown voltage increases, meanwhile the elimination of the gate depletion layer extension to source/drain decreases the gate–source and gate–drain capacitances. The optimized results reveal that the breakdown voltage and the drain saturation current increase about 178% and 46% compared with a conventional HEMT (C-HEMT), respectively. Therefore, the maximum output power density is improved by factor 4.1 in comparison with conventional one. Also, the cut-off frequency of 25.2 GHz and the maximum oscillation frequency of 92.1 GHz for the MIC-HEMT are obtained compared to 13 GHz and 43 GHz for that of the C-HEMT and the minimum figure noise decreased consequently of reducing the gate–drain and gate–source capacitances by about 42% and 40%, respectively. The proposed MIC-HEMT shows a maximum stable gain (MSG) exceeding 24.1 dB at 3.1 GHz which the greatest gain is yet reported for HEMTs, showing the potential of this device for high power RF applications.     

Design and simulation of charge transport in single-electron transistor using TCAD numerical simulator

The ability to control the electron flow of a MOSFET is decreased due to the quantum mechanical effect when scaled down below 50 nm. Hence, A new field of device research is needed to complete this challenge. A device based on Tunneling phenomena is called a single-electron device. In this paper, the most fundamental single-electron device is a single-electron transistor (SET) designed using visual TCAD with a gate length and width of 2 nm. The channel is ultra-thin with a length of 2 nm and a width of 0.005 nm, and the channel thickness is 0.3 nm. Then a Si quantum dot of size 0.5 × 1.nm² is used between the island and the gate. Both the Devices are simulated using the Genius Simulator. And it is found that at room temperature, the device with Si dot is more efficient. The device with Si dot has less capacitance and higher charging efficiency than the device without the Quantum dot.     

强反型区下纳米MOSFET的射频噪声机理分析

为了有效地表征纳米MOSFET强反型区下的射频噪声特性,研究了其噪声建模的方法。在分析45 nm MOSFET射频小信号等效电路参数提取结果的基础上,建立了该器件漏极电流噪声的简洁模型。该模型完整地表征了决定45 nm器件噪声机理的三个组成部分:本征漏极电流噪声、栅极管脚寄生电阻热噪声和栅漏衬底寄生电磁耦合噪声。噪声测量在验证所建模型准确性和精度的同时,还表明:45 nm MOSFET的本征漏极电流噪声为受抑制的散粒噪声,并且随着栅源偏压的降低受抑制性逐渐减弱直至消失。     

部分耗尽结构绝缘体上硅器件的低频噪声特性

针对部分耗尽结构绝缘体上硅(silicon-on-insulator, SOI)器件低频噪声特性展开实验与理论研究. 实验结果表明, 器件低频噪声主要来源于SiO₂-Si界面附近缺陷态对载流子的俘获与释放过程; 基于此理论可提取前栅和背栅氧化层界面附近缺陷态密度分别为8×10¹⁷ eV^-1·cm^-3和2.76×10¹⁷ eV^-1·cm^-3. 基于电荷隧穿机理, 在考虑隧穿削弱因子、隧穿距离与时间常数之间关系的基础上, 提取了前、背栅氧化层内缺陷态密度随空间的分布情况. 此外, SOI器件沟道电流归一化噪声功率谱密度随沟道长度的增加而线性减小, 这表明器件低频噪声主要来源于沟道的闪烁噪声. 最后, 基于电荷耦合效应, 分析了背栅电压对前栅阈值电压、沟道电流以及沟道电流噪声功率谱密度的影响.     

Physics of ultrathin-body silicon-on-insulator Schottky-barrier field-effect transistors

In this article we give an overview over the physical mechanisms involved in the electronic transport in ultrathin-body SOI Schottky-barrier MOSFETs. A strong impact of the SOI and gate oxide thickness on the transistor characteristics is found and explained using experimental as well as simulated data. We elaborate on the influence of scattering in the channel and show that for a significant barrier the on-state current is insensitive to scattering once the mean free path for scattering is larger than a characteristic length scale. In addition, recent efforts to lower the Schottky barrier at the source/drain channel interfaces are presented. Using dopant segregation during silicidation significantly lower effective Schottky barriers can be realized that allow for high performance SB-MOSFET devices. PACS 85.30.Tv; 85.35.-p; 73.30.+y     

Performance assessment of nanoscale Schottky MOSFET as resonant tunnelling device: Non-equilibrium Green’s function formalism

A comprehensive study is performed on the electrical characteristics of Schottky barrier MOSFET (SBMOSFET) in nanoscale regime, by employing the non-equilibrium Green’s function (NEGF) approach. Quantum confinement results in the enhancement of effective Schottky barrier height (SBH). High enough Schottky barriers at the source/drain and the channel form a double barrier profile along the channel that results in the formation of resonance states. We have, for the first time, proposed a resonant tunnelling device based on SBMOSFET in which multiple resonance states are modulated by the gate voltage. Role of essential factors such as temperature, SBH, bias voltage and structural parameters on the feasibility of this device for silicon-based resonant tunnelling applications are extensively studied. Resonant tunnelling appears at low temperatures and low drain voltages and as a result negative differential resistance (NDR) is apparent in the transfer characteristic. Scaling down the gate length to 6 nm increases the peak-to-valley ratio (PVR) of the drain current. As the effective SBH reduces, the curvature of the double barrier profile is gradually diminished. Therefore, multiple resonant states are contributed to the current and consequently resonant tunnelling is smoothed out.     

SiC肖特基源漏MOSFET的阈值电压

SiC肖特基源漏MOSFET的阈值电压不同于传统的MOSFET的阈值电压.在深入分析工作机理的基础上,利用二维模拟软件ISE提取并分析了器件的阈值电压.对SiC肖特基源漏MOSFET的阈值电压给出物理描述,得出当源极载流子主要以场发射方式进入沟道,同时沟道进入强反型状态,此时的栅电压是该器件的阈值电压. 关键词： 碳化硅 肖特基接触 阈值电压     

Simulation analysis of a novel fully depleted SOI MOSFET: Electrical and thermal performance improvement through trapezoidally doped channel and silicon–nitride buried insulator

In this paper, we present a novel nano-scale fully depleted silicon-on-insulator metal-oxide semiconductor field-effect transistor (SOI MOSFET). On-state current increment, leakage current decrement, and self-heating effect improvement are pursued in our proposed structure. The structure makes use of a buried insulator layer which consists of two materials to reduce the self-heating effect. On the other hand, to modify the sub- and super-threshold drain current, vertical trapezoidal doping distribution and additional side gate technique are employed. Our novel transistor is named dual material buried insulator vertical trapezoidal doping SOI MOSFET (DV-SOI MOSFET). We investigate the electrical performance and thermal behavior of the DV-SOI MOSFET using a commercial device simulator. We demonstrate that the proposed structure increases on–off current ratio by orders of magnitude and considerably improves self-heating effect in comparison with the conventional uniform doping fully depleted silicon-on-insulator MOSFET (C-SOI) which uses side gate for better electrical performance.     

Subthreshold swing characteristics of nanowire tunneling FETs with variation in gate coverage and channel diameter

In this study, we demonstrate the simulated subthreshold swing (SS) of silicon nanowire tunneling field-effect transistors (NWTFETs) by varying both the channel diameter from 10 nm to 40 nm and the gate coverage ratio from 30% to 100%. Our simulation work reveals that both a decrease in the channel diameter and an increase in the gate coverage ratio contribute to a reduction in the SS. Additionally, our work shows that the magnitude of the on-current depends linearly on the gate coverage ratio and that the drain current increases with a decrease in the channel diameter. Thus, an NWTFET with a channel diameter of 10 nm and a gate coverage ratio of 100% exhibits superior electrical characteristics over other silicon NWTFETs in that the NWTFET shows a point SS of 22.7 mV/dec, an average SS of 56.3 mV/dec, an on/off current ratio of ∼10¹³, and an on-current of ∼10⁻⁵ A/μm.     

Hot carrier degradation mechanism interpretation by lateral distribution of interface and bulk trap density

We investigated the drain avalanche hot carrier effect (DAHC) of p-type metal-oxide-semiconductor field effect transistor of 0.14 μm channel length (PMOSFET) with SiON gate dielectric. Using three different stress conditions of substrate maximum current, the changes to threshold voltage, maximum transconductance, saturation current and channel leakage current was monitored. Concurrently, the lateral distribution of interface trap density (N_it) and bulk trapped charge density (N_ot) with stress time has been extracted along the 70 nm half channels from gate edge to drain junction, which is the first endeavor in describing charge traps along sub 100 nm short channels. The degradation of the PMOSFET was described by combining electrical property with N_it and N_ot profiles. Hot electron punch through (HEIP) effect was evidenced by negative Not distribution near the drain junction while more severe hot carrier degradation was successfully demonstrated by the empirical power law dependence of the electrical parameters N_it and N_ot. We have studied the evolution of degradation behavior along highly scaled tens of nanometer channel, and N_it and N_ot profile offers systematic study and interpretation of degradation mechanism of hot carrier effect in MOSFET devices.     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

A low specific on-resistance SOI MOSFET with dual gates and recessed drain

A low specific on-resistance (R_on,sp) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R_on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R_on,sp of 4.151 mΩ·cm² (V_GS=15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R_on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes.     

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.     

纳米体硅鳍形场效应晶体管单粒子瞬态中的源漏导通现象

体硅鳍形场效应晶体管(FinFET)是晶体管尺寸缩小到30 nm以下应用最多的结构,其单粒子瞬态产生机理值得关注.利用脉冲激光单粒子效应模拟平台开展了栅长为30, 40, 60, 100 nm Fin FET器件的单粒子瞬态实验,研究FinFET器件单粒子瞬态电流脉冲波形随栅长变化情况;利用计算机辅助设计(technology computer-aided design, TCAD)软件仿真比较电流脉冲产生过程中器件内部电子浓度和电势变化,研究漏电流脉冲波形产生的物理机理.研究表明,不同栅长Fin FET器件瞬态电流脉冲尾部都存在明显的平台区,且平台区电流值随着栅长变短而增大;入射激光在器件沟道区下方体区产生高浓度电子将源漏导通产生导通电流,而源漏导通升高了体区电势,抑制体区高浓度电子扩散,使得导通状态维持时间长,形成平台区电流;尾部平台区由于持续时间长,收集电荷量大,会严重影响器件工作状态和性能.研究结论为纳米Fin FET器件抗辐射加固提供理论支撑.