Pulse coding off-chip learning algorithm for memristive artificial neural network

Memristive neural network has attracted tremendous attention since the memristor array can perform parallel multiply-accumulate calculation (MAC) operations and memory-computation operations as compared with digital CMOS hardware systems. However, owing to the variability of the memristor, the implementation of high-precision neural network in memristive computation units is still difficult. Existing learning algorithms for memristive artificial neural network (ANN) is unable to achieve the performance comparable to high-precision by using CMOS-based system. Here, we propose an algorithm based on off-chip learning for memristive ANN in low precision. Training the ANN in the high-precision in digital CPUs and then quantifying the weight of the network to low precision, the quantified weights are mapped to the memristor arrays based on VTEAM model through using the pulse coding weight-mapping rule. In this work, we execute the inference of trained 5-layers convolution neural network on the memristor arrays and achieve an accuracy close to the inference in the case of high precision (64-bit). Compared with other algorithms-based off-chip learning, the algorithm proposed in the present study can easily implement the mapping process and less influence of the device variability. Our result provides an effective approach to implementing the ANN on the memristive hardware platform.     

Optoelectronic memristor for neuromorphic computing

With the need of the internet of things,big data,and artificial intelligence,creating new computing architecture is greatly desired for handling data-intensive tasks.Human brain can simultaneously process and store information,which would reduce the power consumption while improve the efficiency of computing.Therefore,the development of brainlike intelligent device and the construction of brain-like computation are important breakthroughs in the field of artificial intelligence.Memristor,as the fourth fundamental circuit element,is an ideal synaptic simulator due to its integration of storage and processing characteristics,and very similar activities and the working mechanism to synapses among neurons which are the most numerous components of the brains.In particular,memristive synaptic devices with optoelectronic responding capability have the benefits of storing and processing transmitted optical signals with wide bandwidth,ultrafast data operation speed,low power consumption,and low cross-talk,which is important for building efficient brain-like computing networks.Herein,we review recent progresses in optoelectronic memristor for neuromorphic computing,including the optoelectronic memristive materials,working principles,applications,as well as the current challenges and the future development of the optoelectronic memristor.     

Memristive operations demonstrated by gap-type atomic switches

We demonstrate memristive operations using gap-type Ag₂S atomic switches, in which the growth and shrinkage of an Ag protrusion are controlled by using solid-electrochemical reactions. In addition to conventional memristive operations such as those proposed and demonstrated by resistive random-access memories (ReRAMs) using metal oxide compounds, gap-type Ag₂S atomic switches also show new types of memristive operations by storing information from input signals without changing their output until a sufficient number of signals are inputted. The new types of memristive operations resemble the learning process seen in neuroplasticity, where changes occur in the organization of the human brain as a result of experience.     

一种基于DSP+CPLD的低功耗实时红外成像系统实现方法

非致冷红外焦平面阵列(IRFPA)固有的非均匀性严重制约了系统成像质量,其输出动态范围大和监视器显示输出动态范围小也构成了矛盾。为解决这些问题,采用了复杂可编程逻辑器件(CPLD)设计红外焦平面阵列输出驱动和视频编码芯片的显示时序,以高速低功耗数字信号处理器(DSP)为核心,实现了嵌入式红外图像实时采集与压缩校正硬件系统。提出了一种结合两点校正的灰度直方图统计阈值分段线性压缩变换算法,并进行了实验。结果表明,系统可以实时的对红外图像进行采集和压缩校正,处理后图像的非均匀性得到很好的校正,背景被抑制的同时目标和细节得到了增强。该方案简单可靠,电路功耗较低,可为小型化红外热像仪的研制提供参考。     

Emerging of two-dimensional materials in novel memristor

The rapid development of big-data analytics (BDA), internet of things (IoT) and artificial intelligent Technology (AI) demand outstanding electronic devices and systems with faster processing speed, lower power consumption, and smarter computer architecture. Memristor, as a promising Non-Volatile Memory (NVM) device, can effectively mimic biological synapse, and has been widely studied in recent years. The appearance and development of two-dimensional materials (2D material) accelerate and boost the progress of memristor systems owing to a bunch of the particularity of 2D material compared to conventional transition metal oxides (TMOs), therefore, 2D material-based memristors are called as new-generation intelligent memristors. In this review, the memristive (resistive switching) phenomena and the development of new-generation memristors are demonstrated involving grapheme (GR), transition-metal dichalcogenides (TMDs) and hexagonal boron nitride (h-BN) based memristors. Moreover, the related progress of memristive mechanisms is remarked.     

A multi-scale variational neural network for accelerating motion-compensated whole-heart 3D coronary MR angiography

PurposeTo enable fast reconstruction of undersampled motion-compensated whole-heart 3D coronary magnetic resonance angiography (CMRA) by learning a multi-scale variational neural network (MS-VNN) which allows the acquisition of high-quality 1.2 × 1.2 × 1.2 mm isotropic volumes in a short and predictable scan time.MethodsEighteen healthy subjects and one patient underwent free-breathing 3D CMRA acquisition with variable density spiral-like Cartesian sampling, combined with 2D image navigators for translational motion estimation/compensation. The proposed MS-VNN learns two sets of kernels and activation functions for the magnitude and phase images of the complex-valued data. For the magnitude, a multi-scale approach is applied to better capture the small calibre of the coronaries. Ten subjects were considered for training and validation. Prospectively undersampled motion-compensated data with 5-fold and 9-fold accelerations, from the remaining 9 subjects, were used to evaluate the framework. The proposed approach was compared to Wavelet-based compressed-sensing (CS), conventional VNN, and to an additional fully-sampled (FS) scan.ResultsThe average acquisition time (m:s) was 4:11 for 5-fold, 2:34 for 9-fold acceleration and 18:55 for fully-sampled. Reconstruction time with the proposed MS-VNN was ~14 s. The proposed MS-VNN achieves higher image quality than CS and VNN reconstructions, with quantitative right coronary artery sharpness (CS:43.0%, VNN:43.9%, MS-VNN:47.0%, FS:50.67%) and vessel length (CS:7.4 cm, VNN:7.7 cm, MS-VNN:8.8 cm, FS:9.1 cm) comparable to the FS scan.ConclusionThe proposed MS-VNN enables 5-fold and 9-fold undersampled CMRA acquisitions with comparable image quality that the corresponding fully-sampled scan. The proposed framework achieves extremely fast reconstruction time and does not require tuning of regularization parameters, offering easy integration into clinical workflow.     

众核处理架构在水下航行器相位编码脉冲回波检测中的应用

针对宽带编码脉冲、多输入多输出等新型目标探测体制发展带来的运算量和数据存储需求剧增的问题,根据水下航行器相位编码脉冲回波检测算法的数据级并行特点,提出应用图形处理器(Graphics Processing Unit,GPU)众核处理架构,并从任务分配策略、数据处理流程、GPU硬件资源利用率和存储器访问等角度考虑,设计了算法在GPU上的并行实现框架。利用湖试数据测试了桌面级GPU平台、嵌入式GPU平台与基于多核数字信号处理器(Digital Signal Processor,DSP)的传统航行器信号处理平台的性能,与多核DSP平台相比,嵌入式GPU平台在功耗、运算性能等方面更有优势。研究结果表明采用嵌入式GPU平台可大幅提升每瓦特性能指标并简化系统设计,能满足新型航行器探测系统大数据量、低功耗和实时性的应用需求。      

基于FPGA的嵌入式双核系统设计

随着测试信息处理领域对嵌入式高性能处理需求的快速增长,基于FPGA构建的嵌入式单核系统逐渐暴露出功耗高、并行性差等性能上的不足,针对此问题,提出了基于Xilinx Virtex-5系列FPGA构建嵌入式双核系统的设计方法,搭建了嵌入式双核系统的整体架构,解决了系统中双核之间的数据交互、双核同步以及双核系统配置文件的存储和自动加载等关键问题。最后,通过Virtex-5 ML510开发平台上的实验,验证了设计方法的合理性和正确性,同时,有效的设计方法可以为其它基于FPGA的嵌入式双核系统设计提供可靠参考。     

忆阻器及其阻变机理研究进展

忆阻器是除电阻、电容、电感之外的第四种电路元件,在信息存储、逻辑运算和神经网络等研究领域具有重要的应用前景.本文综述了忆阻器以及忆阻器材料的研究进展,主要介绍了忆阻器的内涵与特征、阻变机理、材料类型以及应用前景,指出了目前忆阻器研究中需要关注的主要问题,并对以后的发展趋势进行了展望.     

事件驱动的无线传感器网络嵌入式操作系统研究

针对无线传感器网络节点能量敏感和多任务的特点,提出了基于事件驱动的嵌入式实时操作系统;采用分层结构的设计思想,构建模块化的系统组件,利用内存控制块链表,实现简易高效的内存管理;基于事件驱动和任务优先级,实现系统低功耗和抢占式的任务调度;实验结果表明,系统功耗低,实时性好。     

基于忆阻器的多涡卷混沌系统及其脉冲同步控制

忆阻器是一种具有记忆功能和纳米级尺寸的非线性元件,作为混沌系统的非线性部分,能够提高混沌系统的信号随机性和复杂度.本文基于增广Lü系统设计了一个三维忆阻混沌系统.仅仅通过改变系统的一个参数,该系统能产生单涡巻、双涡卷和四涡巻的混沌吸引子,说明该系统具有丰富的混沌特性.首先对该忆阻混沌系统的基本动力学行为进行了理论分析和数值仿真,如平衡点稳定性、对称性,Lyapunov指数和维数,分岔图和Poincare截面等.同时,建立了模拟该忆阻混沌系统的SPICE(simulation program with integrated circuit emphasis)电路,给出了不同参数下的电路实验相图,其仿真结果与数值分析相符,从而验证了该忆阻混沌系统的混沌产生能力.由于脉冲同步只在离散时刻传递信息,能量消耗小,同步速度快,易于实现单信道传输,因而在混沌保密通信中更具有实用性.因此,本文从最大Lyapunov指数的角度实现了该忆阻混沌系统的脉冲混沌同步,数值仿真证实了忆阻混沌系统的存在性以及脉冲同步控制的可行性,为进一步研究该忆阻混沌系统在语音保密通信和信息处理中的应用提供了实验基础.     

忆阻Hopfield神经网络动力学分析及其电路实现

提出一种超多稳态忆阻Hopfield神经网络, 它仅包含3个神经元和一个多稳态忆阻突触。从理论上分析神经网络的耗散性和平衡点的稳定性, 并利用分岔图、李雅普诺夫指数谱和相位图等数值方法分析不同忆阻突触耦合强度对神经网络动力学的影响。网络参数固定时, 揭示与初始状态值密切相关的超多稳态性动力学行为。最后, 设计忆阻Hopfield神经网络的模拟等效电路, 并通过PSIM电路仿真验证MATLAB数值仿真结果。     

无线视频传感阵列低复杂度多视点视频编码方案

基于网络中心节点的运动矢量外推技术,提出了一种无线视频传感阵列的低复杂度多视点视频编码方法。该方法考虑到密集型视频传感阵列各视点间通信复杂、布线繁重、且位于各相机节点内的编码器由于计算能力、功耗等限制难以完成复杂的编码过程等特点,利用运动矢量外推逼近技术将大量的运动估计运算从视频编码端移到了网络中心节点,使得新编解码框架下编码器的运动估计的计算复杂度只有传统全搜索运动估计运算的0.3%,降低了系统传感阵列编码端功耗。实验结果表明,该方法的率失真性能比H.264-I帧高出4 dB以上,接近H.264-P帧编码,优于基于Wyner-Ziv理论的分布式多视点视频编码方法。     

基于位相分布限制衍射光学元件的散斑抑制方法

根据散斑产生的机理,利用像素点之间干涉的概念,提出了通过限制光场的位相分布范围来抑制投影图像中散斑对比度的方法.在部分发展散斑的条件下,推导了位相均匀分布情况下的散斑对比度公式,揭示了当相位分布范围在0.6π~2π之间时,散斑对比度随相位分布范围的变化而震荡变化,当把相位分布范围限制在0.6π以下时,散斑对比度会随相位分布范围的减小而迅速下降.建立了理想仿真模型和实际仿真模型来验证该方法的正确性和可行性.在理想仿真模型中,当位相分布范围从2π变到0,所得散斑图样对比度从66.44%降到0;在实际仿真模型中,模拟了实际激光投影系统的光路结构,并运用了两片衍射光学元件,一片用于激光整形匀化,一片用于光场的位相分布范围限制,散斑图样对比度从92.78%降低到2.09%.该方法稳定性高、耗能低、使用元件尺寸小,为全息投影显示的散斑抑制提供了参考.     

Power efficient and colorless PON upstream system using asymmetric clipping optical OFDM and TDMA technologies

Asymmetric clipping optical orthogonal frequency division multiplexing (ACO-OFDM) based time division multiple access (TDMA) Passive Optical Network (PON) upstream transmission architecture is proposed. The system features low power consumption, colorless, and cost effectiveness. Performance and validity of 10 Gb/s upstream transmission are studied and confirmed by simulation. Performance degradation due to interference from rogue Optical Network Unit (ONU) is also studied.     

A generalized model of TiO_x-based memristive devices and its application for image processing

Memristive technology has been widely explored, due to its distinctive properties, such as nonvolatility, high density,versatility, and CMOS compatibility. For memristive devices, a general compact model is highly favorable for the realization of its circuits and applications. In this paper, we propose a novel memristive model of TiO_x-based devices, which considers the negative differential resistance(NDR) behavior. This model is physics-oriented and passes Linn's criteria. It not only exhibits sufficient accuracy(IV characteristics within 1.5% RMS), lower latency(below half the VTEAM model),and preferable generality compared to previous models, but also yields more precise predictions of long-term potentiation/depression(LTP/LTD). Finally, novel methods based on memristive models are proposed for gray sketching and edge detection applications. These methods avoid complex nonlinear functions required by their original counterparts. When the proposed model is utilized in these methods, they achieve increased contrast ratio and accuracy(for gray sketching and edge detection, respectively) compared to the Simmons model. Our results suggest a memristor-based network is a promising candidate to tackle the existing inefficiencies in traditional image processing methods.     

Design and performance evaluation of a metro WDM storage area network with IP datagram support

Storage area networks (SANs) are becoming an important part of optical MANs (metropolitan area networks). Growing storage and business-continuity needs; high-bandwidth, low latency requirements for SANs; storage infrastructure consolidation; and post-9/11 regulatory issues are among the several driving factors to push this trend. We, in this paper, consider a metro wavelength division multiplexing (WDM) SAN that allows the transmission of variable packet size such as Internet protocol (IP) datagram and evaluate its performance by means of discrete-event simulation. The network is based on one fixed transmitter and multiple fixed receivers. Beginning with an introduction and the context of this work, we describe the network and node architectures; and introduce the medium access control (MAC) protocols. Subsequently, using the Poisson and self-similar traffic, we present and discuss performance of the proposed network architecture in terms of throughput and queuing delay under symmetric and asymmetric traffic scenarios. The simulation results suggested that the proposed architecture is suitable for SAN applications which demand low queuing delay and high throughput.     

Optically-controlled resistive switching effectsof CdS nanowire memtransistor

Since it was proposed, memtransistors have been a leading candidate with powerful capabilities in the field of neural morphological networks. A memtransistor is an emerging structure combining the concepts of a memristor and a field-effect transistor with low-dimensional materials, so that both optical excitation and electrical stimuli can be used to modulate the memristive characteristics, which make it a promising multi-terminal hybrid device for synaptic structures. In this paper, a single CdS nanowire memtransistor has been constructed by the micromechanical exfoliation and alignment lithography methods. It is found that the CdS memtransistor has good non-volatile bipolar memristive characteristics, and the corresponding switching ratio is as high as 10⁶ in the dark. While under illumination, the behavior of the CdS memtransistor is similar to that of a transistor or a memristor depending on the incident wavelengths, and the memristive switching ratio varies in the range of 10 to 10⁵ with the increase of the incident wavelength in the visible light range. In addition, the optical power is also found to affect the memristive characteristics of the device. All of these can be attributed to the modulation of the potential barrier by abundant surface states of nanowires and the illumination influences on the carrier concentrations in nanowires.     

Shannon Logic Based Novel QCA Full Adder Design with Energy Dissipation Analysis

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology to replace VLSI-CMOS digital circuits. Due to its attractive features such as low power consumption, ultra-high speed switching, high device density, several digital arithmetic circuits have been proposed. Adder circuit is the most prominent component used for arithmetic operations. All other arithmetic operation can be successively performed using adder circuits. This paper presents Shannon logic based QCA efficient full adder circuit for arithmetic operations. Shannon logic expression with control variables helps the designer to reduce hardware cost; using with minimum foot prints of the chip size. The mathematical models of the proposed adder are verified with the theoretical values. In addition, the energy dissipation losses of the proposed adder are carried out. The energy dissipation calculation is evaluated under the three separate tunneling energy levels, at temperature T = 2K.The proposed adder dissipates less power. QCAPro tool is used for estimating the energy dissipation. In this paper we proposed novel Shannon based adder for arithmetic calculations. This adder has been verified in different aspects like using Boolean algebra besides it power analysis has been calculated. In addition 1-bit full adder has been enhanced to propose 2-bit and 4-bit adder circuits.     

基于Chua电路的四维超混沌忆阻电路

近年来,忆阻混沌电路受到国内外学者的广泛关注,然而目前四维忆阻系统往往只存在普通混沌(仅有一个正Lyapunov指数),本文通过用忆阻替换Chua电路中电阻的新途径,得出一个简单的四维忆阻电路,与仅含有限个孤立不稳定平衡点的大多已知系统不同,本系统存在无穷多个稳定和不稳定平衡点,研究发现该系统存在着极限环、混沌、超混沌等丰富的复杂行为,通过进一步数值分析和电路仿真实验,证实了超混沌吸引子的存在,从而解决了关于四维忆阻电路是否存在超混沌的疑问。