The charge storage of the nc—Si layer

Sandwiched structures (a-SiN_x/a-Si/a-SiN_x) have been fabricated by the plasma enhanced chemical vapour deposition technique. A Si nanocrystal (nc-Si) layer was formed by crystallization of an a-Si layer according to the constrained crystallization principle after quasi-static thermal annealing at 1100℃ for 30 min. Transmission electron microscopy (TEM) and Raman scattering spectroscopy clearly demonstrated that nc-Si grains were formed in the as-deposited a-Si layer after annealing. The density of nc-Si grains is about 10¹¹cm^-2 as shown by TEM photographs. Using capacitance－voltage (C－V) measurements we investigated the electrical characteristics of the sandwiched structures. The charge storage phenomenon of the nc-Si layer was observed from the shift of flat-band voltage (V_FB) in C－V curves at a high frequency (1 MHz). We estimated the density of nc-Si grains to be about 10¹¹cm^-2 from the shift value of V_FB, which is in agreement with the result of TEM photographs. At the same time, we found that the shift of V_FB increased with the increase of the applied constant dc voltage or the thickness of the nc-Si layer.     

Influence of lithium phosphate concentration and temperature on the electrical conduction of (76V2O5-24P2O5)1−X (Li3PO4)X glasses

Characterization of the (76V₂O₅-24P₂O₅)_1−X (Li₃PO₅)_X, where X=0.0,0.01,0.02,0.10 and 0.15, glass has been done using X-ray diffraction and differential thermal analysis (DTA). The dc conductivity of the glass samples was studied over a temperature range from 300 to 593 K. The temperature dependence of dc conductivity shows two regions. One at relatively high temperature range, above θ_D/2, and the other at relatively low temperature range, below θ_D/2. The I-V characteristics of the glasses have been studied as a function of both temperature and Li₃PO₄ content. The I-V characteristics exhibits threshold switching with differential negative resistance. It's found that both the threshold voltage (V_th) and threshold current (I_th) are dependent on the temperature and lithium phosphate concentration.     

Selective floating gate non‐volatile paper memory transistor

Here we report the performance of a selective floating gate (V_GS) n‐type non‐volatile memory paper field‐effect transistor. The paper dielectric exhibits a spontaneous polarization of about 1 mCm^–2 and GIZO and IZO amorphous oxides are used respectively as the channel and the gate layers. The drain and source regions are based in continuous conductive thin films that promote the integration of fibres coated with the active semiconductor. The floating memory transistor writes, reads and erases the stored information with retention times above 14500 h, and is selective (for V_GS > 5 ± 0.1 V). That is, to erase stored information a symmetric pulse to the one used to write must be utilized, allowing to store in the same space different information. (© 2009 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Electrical behavior of amorphous indium–gallium–zinc oxide thin film transistors by embedding Au nanoparticles in the channel layer

We reported the effects on the electrical behavior of amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) after introducing various positions and sizes of Au nanoparticles (NPs) in the channel layer. These TFTs showed an off-current increase and threshold voltage (V_th) shift compared to conventional a-IGZO TFTs. The effects of Au NPs are explained to form the carrier conduction path which causes the current leakage in the channel layer, and act as either electron injection sites or trap sites. Therefore, this study demonstrates that the optimized control of size and position of Au NPs in the channel layer is crucial for its application in the electrical stability improvement and V_th control of a-IGZO TFTs.     

Memory effect of pentacene field-effect transistors with embedded monolayer of semiconductor colloidal nano-dots

We demonstrate memory effect of pentacene-based field-effect transistors (FETs) in which CdSe/ZnS colloidal nano-dots (NDs) are embedded. The colloidal NDs were dispersed in chloroform, and spread over a water surface to form monolayer of NDs. Then, they were transferred onto a 30-nm-thick poly(methyl methacrylate) (PMMA) surface by horizontal lifting method, and a 30-nm-thick pentacene film was deposited as an active layer to fabricate FETs. The threshold voltage (V_th) was shifted by ∼10 V after a writing voltage of 70–100 V was applied to the gate electrode of the memory-FETs. On the other hand, such a large shift of V_th was not observed for reference pentacene-FETs without NDs. We consider that the large shift of V_th is due to electrons trapped in the NDs at the interface of pentacene and PMMA layers.     

Double‐layer channel structure based ZnO thin‐film transistor grown by atomic layer deposition

A double channel structure has been used by depositing a thin amorphous‐AlZnO (a‐AZO) layer grown by atomic layer deposition between a ZnO channel and a gate dielectric to enhance the electrical stability. The effect of the a‐AZO layer on the electrical stability of a‐AZO/ZnO thin‐film transistors (TFTs) has been investigated under positive gate bias and temperature stress test. The use of the a‐AZO layer with 5 nm thickness resulted in enhanced subthreshold swing and decreased V_th shift under positive gate bias/temperature stress. In addition, the falling rate of the oxide TFT using a‐AZO/ ZnO double channel had a larger value (0.35 eV/V) than that of pure ZnO TFT (0.24 eV/V). These results suggest that the interface trap density between dielectric and channel was reduced by inserting a‐AZO layer at the interface between the channel and the gate insulator, compared with pure ZnO channel. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Silicon nanoparticle charge trapping memory cell

A charge trapping memory with 2 nm silicon nanoparticles (Si NPs) is demonstrated. A zinc oxide (ZnO) active layer is deposited by atomic layer deposition (ALD), preceded by Al₂O₃ which acts as the gate, blocking and tunneling oxide. Spin coating technique is used to deposit Si NPs across the sample between Al₂O₃ steps. The Si nanoparticle memory exhibits a threshold voltage (V_t) shift of 2.9 V at a negative programming voltage of –10 V indicating that holes are emitted from channel to charge trapping layer. The negligible measured V_t shift without the nanoparticles and the good re‐ tention of charges (>10 years) with Si NPs confirm that the Si NPs act as deep energy states within the bandgap of the Al₂O₃ layer. In order to determine the mechanism for hole emission, we study the effect of the electric field across the tunnel oxide on the magnitude and trend of the V_t shift. The V_t shift is only achieved at electric fields above 1 MV/cm. This high field indicates that tunneling is the main mechanism. More specifically, phonon‐assisted tunneling (PAT) dominates at electric fields between 1.2 MV/cm < E < 2.1 MV/cm, while Fowler–Nordheim tunneling leads at higher fields (E > 2.1 MV/cm). (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Switching phenomenon and optical properties of Se85Te10Bi5 films

Se₈₅Te₁₀Bi₅ films of different thicknesses ranging from 126 to 512 nm have been prepared. Energy-dispersive X-ray (EDX) spectroscopy technique showed that films are nearly stoichiometric. X-ray diffraction (XRD) measurements have showed that the Se₈₅Te₁₀Bi₅ films were amorphous. Electrical conduction activation energy (ΔE_σ) for the obtained films is found to be 0.662 eV independent of thickness in the investigated range. Investigation of the current voltage (I-V) characteristics in amorphous Se₈₅Te₁₀Bi₅ films reveals that it is typical for a memory switch. The switching voltage V_th increases with the increase of the thickness and decreases exponentially with temperature in the range from 298 to 383 K. The switching voltage activation energy (ε) calculated from the temperature dependence of V_th is found to be 0.325 eV. The switching phenomenon in amorphous Se₈₅Te₁₀Bi₅ films is explained according to an electrothermal model for the switching process. The optical constants, the refractive index (n) and the absorption index (k) have been determined from transmittance (T) and reflectance (R) of Se₈₅Te₁₀Bi₅ films. Allowed non-direct transitions with an optical energy gap (E_g^opt) of 1.33 eV have been obtained. ΔE_σ is almost half the obtained value of E_g^opt, which suggested band to band conduction as indicated by Davis and Mott.     

Memory switching of germanium tellurium amorphous semiconductor

The dc conductivity and switching properties of amorphous GeTe thin film of thickness 262 nm are investigated in the temperature range 303-373 K. The activation energy ΔE_σ, the room temperature electrical conductivity σ_RT and the pre-exponential factor σ₀ were measured and validated for the tested sample. The conduction activation energy ΔE_σ is calculated. The I-V characteristic curves of the thin film samples showing a memory switching at the turnover point (TOP) from high resistance state (OFF state) to the negative differential resistance state (NDRS) (ON state). It is found that the mean values of the threshold electrical field E_th decreased exponentially with increasing temperatures in the investigated range. The switching activation energy ΔE_th is calculated. Measurements of the dissipated threshold power P_th and the threshold resistance R_th were carried out at TOP point at different temperatures of the samples. The activation energies ΔE_R and ΔE_P caused by resistance and power respectively are deduced. The results obtained support thermal model for initiating switching process in this system.     

(n)nc-Si：H/(p)c-Si异质结中载流子输运性质的研究

采用常规等离子体增强化学气相沉积工艺,以高H₂稀释的SiH₄作为反应气体源和PH₃作为磷原子的掺杂剂,在p型(100)单晶硅((p)c-Si)衬底上, 成功地生长了施主掺杂型纳米硅膜((n)nc-Si:H),进而制备了(n)nc-Si:H/(p)c-Si异质结,并在230—420Ｋ温度范围内实验研究了该异质结的Ｉ-Ｖ特性.结果表明,(n)nc-Si:H/(p)c- Si异质结为一典型的突变异质结构,具有良好的温度稳定性和整流特性.正向偏压下 关键词： (n)nc-Si:H/(p)c-Si异质结 能带模型 电流输运机构 温度特性     

Memory characteristics and tunneling mechanism of Pt nano-crystals embedded in HfAlOx films for nonvolatile flash memory devices

A non-volatile flash memory device based on metal oxide semiconductor (MOS) capacitor structure has been fabricated using platinum nano-crystals(Pt–NCs) as storage units embedded in HfAlO_x high-k tunneling layers. Its memory characteristics and tunneling mechanism are characterized by capacitance–voltage(C–V) and flat-band voltage-time(ΔV_FB-T) measurements. A 6.5 V flat-band voltage (memory window) corresponding to the stored charge density of 2.29 × 10¹³ cm⁻² and about 88% stored electron reserved after apply ±8 V program or erase voltage for 10⁵ s at high frequency of 1 MHz was demonstrated. Investigation of leakage current–voltage(J–V) indicated that defects-enhanced Pool-Frenkel tunneling plays an important role in the tunneling mechanism for the storage charges. Hence, the Pt–NCs and HfAlO_x based MOS structure has a promising application in non-volatile flash memory devices.     

Effect of channel thickness on electrical performance of amorphous IGZO thin-film transistor with atomic layer deposited alumina oxide dielectric

We have investigated the electrical performance of amorphous indium–gallium–zinc oxide (α-IGZO) thin-film transistors with various channel thicknesses. It is observed that when the α-IGZO thickness increases, the threshold voltage decreases as reported at other researches. The intrinsic field-effect mobility as high as 11.1 cm²/Vs and sub threshold slope as low as ∼0.2 V/decade are independent on the thickness of α-IGZO channel, which indicate the excellent interface between α-IGZO and atomic layer deposited Al₂O₃ dielectric even for the case with α-IGZO thickness as thin as 10 nm. However, the source and drain series resistances increased with increasing of α-IGZO channel thickness, which results in the apparent field-effect mobility decreasing. The threshold voltage shift (ΔV_th) under negative bias stress (NBS) and negative bias illumination stress (NBIS) were investigated, also. The hump-effect in the sub threshold region under NBS and threshold voltage shift to negative position under NBIS were enhanced with decreasing of α-IGZO channel thickness, owing to the enhancement of vertical electrical field in channel.     

控制氧化层对双势垒纳米硅浮栅存储结构性能的影响

在等离子体增强化学气相沉积(PECVD)系统中,利用逐层淀积非晶硅(a-Si)和等离子体氧化相结合的方法制备二氧化硅(SiO₂)介质层.电容电压(C-V)和电导电压(G-V)测量结果表明：利用该方法在低温(250 ℃)条件下制备的SiO₂介质层均匀致密,其固定氧化物电荷和界面态密度分别为9×10¹¹cm^-2和2×10¹¹cm^-2·eV^-1,击穿场强达4.6 MV/cm,与热氧化形成的SiO₂介质层的性质相当.将该SiO₂介质层作为控制氧化层应用在双势垒纳米硅(nc-Si)浮栅存储结构中,通过调节控制氧化层的厚度,有效阻止栅电极与nc-Si之间的电荷交换,延长存储时间,使存储性能得到明显改善. 关键词： 等离子体氧化 二氧化硅 纳米硅 控制氧化层     

Hot-carrier degradation for 90nm gate length LDD-NMOSFET with ultra-thin gate oxide under low gate voltage stress

The hot-carrier degradation for 90~nm gate length lightly-doped drain (LDD) NMOSFET with ultra-thin (1.4~nm) gate oxide under the low gate voltage (LGV) (at V_g=V_th, where V_th is the threshold voltage) stress has been investigated. It is found that the drain current decreases and the threshold voltage increases after the LGV (V_g=V_th stress. The results are opposite to the degradation phenomena of conventional NMOSFET for the case of this stress. By analysing the gate-induced drain leakage (GIDL) current before and after stresses, it is confirmed that under the LGV stress in ultra-short gate LDD-NMOSFET with ultra-thin gate oxide, the hot holes are trapped at interface in the LDD region and cannot shorten the channel to mask the influence of interface states as those in conventional NMOSFET do, which leads to the different degradation phenomena from those of the conventional NMOS devices. This paper also discusses the degradation in the 90~nm gate length LDD-NMOSFET with 1.4~nm gate oxide under the LGV stress at V_g=V_th with various drain biases. Experimental results show that the degradation slopes (n) range from 0.21 to 0.41. The value of n is less than that of conventional MOSFET (0.5-0.6) and also that of the long gate length LDD MOSFET (\sim0.8).     

Electrical characteristics of poly(methylsilsesquioxane) thin films for non-volatile memory

In this communication the electrical characteristics of poly(methylsilsesquioxane) (PMSSQ) thin films and the possibility of charge storage in the Au nanoparticle embedded PMSSQ film base memory element have been studied. PMSSQ films were sandwiched between Al and Si electrodes to fabricate metal-polymer-semiconductor (MPS) structures. The conduction mechanism in PMSSQ films has been investigated. The charge transport mechanism appears to be space charge limited current (SCLC) at the higher-voltage region. Various electrical parameters such as reverse saturation current, barrier height, ideality factor, rectification ratio, shunt and series resistance and charge carrier mobility in PMSSQ have been determined. C-V analysis is performed to confirm the memory effect for Au nanoparticles embedded MPS structures. A definite clockwise hysteresis is observed which indicates the possibility of charge storage in the Au nanoparticles embedded PMSSQ film.     

On the effects of NBTI degradation in p-MOSFET devices

This paper presents the effects of interface trap concentration and threshold voltage shift on NBTI degradation in p-MOSFETs. To explore the degradation mechanisms, transistors having an EOT of 1.1 nm and 5 nm were simulated by applying various stress conditions. The NBTI degradation mechanism was studied by varying the gate voltage, temperature and substrate doping level. The simulations show NBTI degradation in terms of the threshold voltage shift, ΔV_th and number of interface traps, ΔN_it. The simulation results show an improved degradation trend in terms of ΔV_th and ΔN_it when the substrate doping level is increased.     

Photo-induced bias of the hysteresis loop in ferrites at room temperature with long-time memory

New photo-magnetic effects with an indefinitely long-time memory are found at room temperature in the epitaxial Mg_0.75Mn_0.21Co_0.04Fe₂O₄ ferrite film. Illumination of the ferrimagnetic material with low-intensity (0.4 W cm⁻²) circularly polarized light with or without a static magnetic field in the Faraday effect geometry results in a number of nonlinear effects in both space and time. In a uniform crystal with cubic symmetry, the long-lived photo-induced magnetization (PIM) with a unidirectional anisotropy appears along the direction of the incoming light. The effects depend on a combination of magnetic field H and the helicity of circularly polarized light σ. Two combinations H⁺,σ⁺ and H⁻,σ⁻ lead to a photo-induced unidirectional anisotropy with a shift of the hysteresis loop along an applied field and a change in loop parameters. The loop contracts by a factor of two, the shift of the mid-point H_sh increases by factor of five surpassing the coercivity H_c, the coercivity H_c1 and remanence M_r1 (for decreasing applied field) reverse the sign, increasing by 9 Oe and reducing by a factor of 4.5, respectively. The effects cannot be erased by a conventional demagnetization (using an AC current that is reduced to zero amplitude), but can be removed using an illumination with two other combinations (H⁺,σ⁻ and H⁻,σ⁺) as well as by heating at temperatures higher than the Curie temperature. This long-lived room-temperature memory effect may arise from the formation of complex photo-induced defects including photo-induced magnetic polarons. The possible mechanisms responsible for the appearance of a room-temperature photo-induced unidirectional anisotropy with a long-lived memory are discussed. These new photo-magnetic effects may find an application in magneto-optical memory devices.     

氮化硅介质中双层纳米硅薄膜的两级电荷存储

研究镶嵌在超薄非晶氮化硅(a-SiN_x)层之间的双层纳米硅(nc-Si)的电荷存储现象.利用等离子体增强化学气相淀积(PECVD)技术在硅衬底上制备a-SiN_x/a-Si/a-SiN_x/a-Si/a-SiN_x多层薄膜结构.采用常规热退火方法使非晶硅(a-Si)层晶化，形成包含双层nc-Si的金属-氮化物-半导体(MIS)结构.通过电容电压(C-V)特性测量，观测到该结构中由于电荷存储引起的C-V回滞现象，并在室温下成功观察到载流子基于Fowler-Nordheim(F-N)隧穿注入到第一层、第二层nc-Si的两级电荷存储状态.结合电流电压(I-V)特性的测量，对电荷存储的机理进行了深入分析. 关键词： 纳米硅 氮化硅 电容电压法 电流电压法     

Effects of hydrogen plasma annealing on the luminescence from a-Si:H/SiO2 and nc-Si/SiO2 multilayers

Effects of post-hydrogen plasma annealing (HPA) on a-Si:H/SiO₂ and nc-Si/SiO₂ multilayers have been investigated and compared. It is found that photoluminescence (PL) from hydrogen-passivated samples was improved due to the reduction of non-radiative recombination defects. Some interesting difference is that during HPA, atomic hydrogen can directly passivate defects of a-Si:H/SiO₂, which results in the reappearance of luminescence band at 760 nm, while for nc-Si/SiO₂, hydrogen passivation requires additional thermal annealing after nc-Si/SiO₂ multilayer was treated by HPA. It is indicated that higher atomic mobility is needed to passivate defects at nc-Si/SiO₂ interface compared with a-Si:H/SiO₂ interface.     

Electrical properties of carbon-nanotube-network transistors in air after gamma irradiation

We experimentally evaluate the electrical properties of carbon nanotube (CNT)-network transistors before and after ⁶⁰Co gamma-ray irradiation up to 50 kGy in an air environment. When the total dose is increased, the degree of the threshold voltage (V_th) shift towards positive gate voltages in the drain current–gate voltage (I_D–V_GS) characteristics decreases for total irradiation doses above 30 kGy, although it is constant below 30 kGy. From our analysis of the I_D–V_GS characteristics along with micro-Raman spectroscopy, the gamma-ray irradiation does not change the structure of the CNT network channel for total doses up to 50 kGy; it instead generates charge traps near the CNT/SiO₂ gate insulator interfaces. These traps are located within the SiO₂ layer and/or the adsorbate on the device surface. The positively charged traps near the CNT/SiO₂ interface contribute less to the V_th shift than the interface dipoles at the CNT/metal electrode interfaces and the segment of the CNT network channel below doses of 30 kGy, while the contribution of the charge traps increases for total doses above 30 kGy. Our findings indicate the possibility of the application of CNT-network transistors as radiation detectors suitable for use in air for radiation doses above 30 kGy.