Junction barrier Schottky rectifier with an improved P-well region

<正>A junction barrier Schottky（JBS） rectifier with an improved P-well on 4H-SiC is proposed to improve the V_F-I_R trade-off and the breakdown voltage.The reverse current density of the proposed JBS rectifier at 300 K and 800 V is about 3.3×10^-8 times that of the common JBS rectifier at no expense of the forward voltage drop.This is because the depletion layer thickness in the P-well region at the same reverse voltage is larger than in the P⁺ grid,resulting in a lower spreading current and tunneling current.As a result,the breakdown voltage of the proposed JBS rectifier is over 1.6 kV,that is about 0.8 times more than that of the common JBS rectifier due to the uniform electric field.Although the series resistance of the proposed JBS rectifier is a little larger than that of the common JBS rectifier,the figure of merit（FOM） of the proposed JBS rectifier is about 2.9 times that of the common JBS rectifier.Based on simulating the values of susceptibility of the two JBS rectifiers to electrostatic discharge（ESD） in the human body model（HBM） circuits,the failure energy of the proposed JBS rectifier increases 17%compared with that of the common JBS rectifier.     

High density Al2O3/TaN-based metal--insulator-- metal capacitors in application to radio frequency integrated circuits

Metal-insulator-metal （MIM） capacitors with atomic-layer-deposited Al2O3 dielectric and reactively sputtered TaN electrodes in application to radio frequency integrated circuits have been characterized electrically. The capacitors exhibit a high density of about 6.05 fF/μm^2, a small leakage current of 4.8 × 10^-8 A/cm^2 at 3 V, a high breakdown electric field of 8.61 MV/cm as well as acceptable voltage coefficients of capacitance （VCCs） of 795 ppm/V2 and 268ppm/V at 1 MHz. The observed properties should be attributed to high-quality Al2O3 film and chemically stable TaN electrodes. Further, a logarithmically linear relationship between quadratic VCC and frequency is observed due to the change of relaxation time with carrier mobility in the dielectric. The conduction mechanism in the high field ranges is dominated by the Poole-Frenkel emission, and the leakage current in the low field ranges is likely to be associated with trap-assisted tunnelling. Meanwhile, the Al2O3 dielectric presents charge trapping under low voltage stresses, and defect generation under high voltage stresses, and it has a hard-breakdown performance.     

具有半绝缘多晶硅完全三维超结横向功率器件

为了突破传统LDMOS (lateral double-diffused MOSFET)器件击穿电压与比导通电阻的硅极限的2.5 次方关系, 降低LDMOS器件的功率损耗, 提高功率集成电路的功率驱动能力, 提出了一种具有半绝缘多晶硅SIPOS (semi-insulating poly silicon)覆盖的完全3 D-RESURF (three-dimensional reduced surface field)新型Super Junction-LDMOS结构(SIPOS SJ-LDMOS). 这种结构利用SIPOS的电场调制作用使SJ-LDMOS的表面电场分布均匀, 将器件单位长度的耐压量提高到19.4 V/μupm; 覆盖于漂移区表面的SIPOS使SJ-LDMOS沿三维方向均受到电场调制, 实现了LDMOS的完全3 D-RESURF效应, 使更高浓度的漂移区完全耗尽而达到高的击穿电压; 当器件开态工作时, 覆盖于薄场氧化层表面的SIPOS的电场作用使SJ-LDMOS的漂移区表面形成多数载流子积累, 器件比导通电阻降低. 利用器件仿真软件ISE分析获得, 当SIPOS SJ-LDMOS的击穿电压为388 V时, 比导通电阻为20.87 mΩ·cm², 相同结构参数条件下, N-buffer SJ-LDMOS的击穿电压为287 V, 比导通电阻为31.14 mΩ·cm²; 一般SJ-LDMOS 的击穿电压仅为180 V, 比导通电阻为71.82 mΩ·cm².     

Modeling of 4H--SiC multi-floating-junction Schottky barrier diode

This paper develops a new and easy to implement analytical model for the specific on-resistance and electric field distribution along the critical path for 4H-SiC multi-floating junction Schottky barrier diode. Considering the charge compensation effects by the multilayer of buried opposite doped regions, it improves the breakdown voltage a lot in comparison with conventional one with the same on-resistance. The forward resistance of the floating junction Schottky barrier diode consists of several components and the electric field can be understood with superposition concept, both are consistent with MEDICI simulation results. Moreover, device parameters are optimized and the analyses show that in comparison with one layer floating junction, multilayer of floating junction layer is an effective way to increase the device performance when specific resistance and the breakdown voltage are traded off. The results show that the specific resistance increases 3.2 mΩ·cm 2 and breakdown voltage increases 422 V with an additional floating junction for the given structure.     

Edge termination study and fabrication of a 4Hben SiC junction barrier Schottky diode

The 4H-SiC junction barrier Schottky (JBS) diodes terminated by field guard rings and offset field plate are designed, fabricated and characterized. It is shown experimentally that a 3-μm P-type implantation window spacing gives an optimum trade-off between forward drop voltage and leakage current density for these diodes, yielding a specific on-resistance of 8.3 mΩ·cm². A JBS diode with a turn-on voltage of 0.65 V and a reverse current density less than 1 A/cm² under 500 V is fabricated, and the reverse recovery time is tested to be 80 ns, and the peak reverse current is 28.1 mA. Temperature-dependent characteristics are also studied in a temperature range of 75 ℃-200 ℃. The diode shows a stable Schottky barrier height of up to 200 ℃ and a stable operation under a continuous forward current of 100 A/cm².     

Experimental and numerical analyses of high voltage 4H-SiC junction barrier Schottky rectifiers with linearly graded field limiting ring

This paper describes the successful fabrication of 4H-SiC junction barrier Schottky(JBS) rectifiers with a linearly graded field limiting ring(LG-FLR). Linearly variable ring spacings for the FLR termination are applied to improve the blocking voltage by reducing the peak surface electric field at the edge termination region, which acts like a variable lateral doping profile resulting in a gradual field distribution. The experimental results demonstrate a breakdown voltage of 5 kV at the reverse leakage current density of 2 mA/cm2(about 80% of the theoretical value). Detailed numerical simulations show that the proposed termination structure provides a uniform electric field profile compared to the conventional FLR termination, which is responsible for 45% improvement in the reverse blocking voltage despite a 3.7% longer total termination length.     

Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET

A novel voltage-withstand substrate with high-K (HK, k>3.9, k is the relative permittivity) dielectric and low specific on-resistance (R_on,sp) bulk-silicon, high-voltage LDMOS (HKLR LDMOS) is proposed in this paper. The high-K dielectric and highly doped interface N⁺-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration (N_d) and reshape the electric field distribution. The highly doped N⁺-layer under the high-K dielectric acts as a low resistance path to reduce the R_on,sp. The new device with the high breakdown voltage (BV), the low R_on,sp, and the excellent figure of merit (FOM=BV²/R_on,sp) is obtained. The BV of HKLR LDMOS is 534 V, R_on,sp is 70.6 mΩ·cm², and FOM is 4.039 MW·cm^-2.     

Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures

Current transport mechanism in Ni-germanide/n-type Ge Schottky diodes is investigated using current--voltage characterisation technique with annealing temperatures from 300~\duto 500~\du. Based on the current transport model, a simple method to extract parameters of the NiGe/Ge diode is presented by using the $I$--$V$ characteristics. Parameters of NiGe/n-type Ge Schottky diodes fabricated for testing in this paper are as follows: the ideality factor $n$, the series resistance $R_{\rm s}$, the zero-field barrier height $\phi _{\rm b0}$, the interface state density $D_{\rm it}$, and the interfacial layer capacitance $C_{\rm i}$. It is found that the ideality factor $n$ of the diode increases with the increase of annealing temperature. As the temperature increases, the interface defects from the sputtering damage and the penetration of metallic states into the Ge energy gap are passivated, thus improving the junction quality. However, the undesirable crystallisations of Ni-germanide are observed together with NiGe at a temperature higher than 400~\du. Depositing a very thin ($\sim $1~nm) heavily Ge-doped $n^{+}$ Ge intermediate layer can improve the NiGe film morphology significantly.     

具有p-GaN岛状埋层耐压结构的横向AlGaN/GaN高电子迁移率晶体管

GaN基高电子迁移率晶体管(HEMT)相对较低的击穿电压严重限制了其大功率应用.为了进一步改善器件的击穿特性,通过在n-GaN外延缓冲层中引入六个等间距p-GaN岛掩埋缓冲层(PIBL)构成p-n结,提出一种基于p-GaN埋层结构的新型高耐压AlGaN/GaN HEMT器件结构.Sentaurus TCAD仿真结果表明,在关态高漏极电压状态下,p-GaN埋层引入的多个反向p-n结不仅能够有效调制PIBL AlGaN/GaN HEMT的表面电场和体电场分布,而且对于缓冲层泄漏电流有一定的抑制作用,这保证了栅漏间距为10μm的PIBL HEMT能够达到超过1700 V的高击穿电压(BV),是常规结构AlGaN/GaN HEMT击穿电压(580 V)的3倍.同时,PIBL结构AlGaN/GaN HEMT的特征导通电阻仅为1.47 m?·cm~2,因此获得了高达1966 MW·cm~(-2)的品质因数(FOM=BV~2/R_(on,sp)).相比于常规的AlGaN/GaN HEMT,基于新型p-GaN埋岛结构的HEMT器件在保持较低特征导通电阻的同时具有更高的击穿电压,这使得该结构在高功率电力电子器件领域具有很好的应用前景.     

High energy electron radiation effect on Ni/4H-SiC SBD and Ohmic contact

The Ni/4H-SiC Schottky barrier diodes (SBDs) and transfer length method (TLM) test patterns of Ni/4H-SiC Ohmic contacts were fabricated, and irradiated with 1~MeV electrons up to a dose of 3.43× 10¹⁴~e/cm^-2. After radiation, the forward currents of the SBDs at 2~V decreased by about 50%, and the reverse currents at -200~V increased by less than 30%. Schottky barrier height (φ _B ) of the Ni/4H-SiC SBD increased from 1.20~eV to 1.21~eV under 0~V irradiation bias, and decreased from 1.25~eV to 1.19~eV under -30~V irradiation bias. The degradation of φ _B could be explained by the variation of interface states of Schottky contacts. The on-state resistance (R_s) and the reverse current increased with the dose, which can be ascribed to the radiation defects in bulk material. The specific contact resistance (\rho_c) of the Ni/SiC Ohmic contact increased from 5.11× 10⁵~Ωega.cm² to 2.97× 10^-4~Ωega.cm².     

Dynamical study on charge injection and transport in a metal/polythiophene/metal structure

The dynamical process of charge injection from metal electrode to a nondegenerate polymer in a metal/polythiophene （PT）/metal structure has been investigated by using a nonadiabatic dynamic approach. It is found that the injected charges form wave packets due to the strong electron-lattice interaction in PT. We demonstrate that the dynamical formation of the wave packet sensitively depends on the strength of applied voltage, the electric field, and the contact between PT and electrode. At a strength of the electric field more than 3.0 × 10^4 V/cm, the carriers can be ejected from the PT into the right electrode. At an electric field more than 3.0 × 10^5 V/cm, the wave packet cannot form while it moves rapidly to the right PT/metal interface. It is shown that the ejected quantity of charge is noninteger.     

High energy electron radiation effect on Ni and Ti/4H-SiCSchottky barrier diode at room temperature

This paper reports that Ni and Ti/4H-SiC Schottky barrier diodes (SBDs) were fabricated and irradiated with 1~MeV electrons up to a dose of 3.43×10¹⁴~e/cm². After radiation, the Schottky barrier height φ _B of the Ni/4H-SiC SBD increased from 1.20~eV to 1.21~eV, but decreased from 0.95~eV to 0.94~eV for the Ti/4H-SiC SBD. The degradation of φ _B could be explained by interface states of changed Schottky contacts. The on-state resistance R_S of both diodes increased with the dose, which can be ascribed to the radiation defects. The reverse current of the Ni/4H-SiC SBD slightly increased, but for the Ti/4H-SiC SBD it basically remained the same. At room temperature, φ _B of the diodes recovered completely after one week, and the R_S partly recovered.     

铝-金刚石界面电子特性与界面肖特基势垒的杂化密度泛函理论HSE06的研究

宽带隙半导体金刚石具有突出的电学与热学特性,近年来,基于金刚石的高频大功率器件受到广泛关注,对于金属-金刚石肖特基结而言,具有较高的击穿电压和较小的串联电阻,所以金属-金刚石这种金半结具有非常好的发展前景.本文通过第一性原理方法去研究金属铝-金刚石界面电子特性与肖特基势垒的高度.界面附近原子轨道的投影态密度的计算表明:金属诱导带隙态会在金刚石一侧产生,并且具有典型的局域化特征,同时可以发现电子电荷转移使得Fermi能级在金刚石一侧有所提升.电子电荷在界面的重新分布促使界面形成新的化学键,使得金属铝-氢化金刚石形成稳定的金半结.特别地,我们通过计算平均静电势的方法得到金属铝-氢化金刚石界面的势垒高度为1.03 eV,该值与金属诱导带隙态唯像模型计算的结果非常接近,也与实验值符合得很好.本文的研究可为金属-金刚石肖特基结二极管的研究奠定理论基础,也可为金刚石基金半结大功率器件的研究提供理论参考.     

Hybrid-anode structure designed for a high-performance quasi-vertical GaN Schottky barrier diode

A quasi-vertical GaN Schottky barrier diode with a hybrid anode structure is proposed to trade off the on-resistance and the breakdown voltage. By inserting a SiN dielectric between the anode metal with a relatively small length, it suppresses the electric field crowding effect without presenting an obvious effect on the forward characteristics. The enhanced breakdown voltage is ascribed to the charge-coupling effect between the insulation dielectric layer and GaN. On the other hand, the current density is decreased beneath the dielectric layer with the increasing length of the SiN, resulting in a high on-resistance. Furthermore, the introduction of the field plate on the side wall forms an metal-oxide-semiconductor (MOS) channel and decreases the series resistance, but also shows an obvious electric field crowding effect at the bottom of the mesa due to the quasi-vertical structure.     

Simulation study of a mixed terminal structure for 4H-SiC merged PiN/Schottky diode

In this paper, a mixed terminal structure for the 4H-SiC merged PiN/Schottky diode (MPS) is investigated, which is a combination of a field plate, a junction termination extension and floating limiting rings. Optimization is performed on the terminal structure by using the ISE-TCAD. Further analysis shows that this structure can greatly reduce the sensitivity of the breakdown voltage to the doping concentration and can effectively suppress the effect of the interface charge compared with the structure of the junction termination extension. At the same time, the 4H-SiC MPS with this termination structure can reach a high and stable breakdown voltage.     

新型缓冲层分区电场调制横向双扩散超结功率器件

为了突破传统横向双扩散金属-氧化物-半导体器件(lateral double-diffused MOSFET)击穿电压与比导通电阻的极限关系,本文在缓冲层横向双扩散超结功率器件(super junction LDMOS-SJ LDMOS)结构基础上,提出了具有缓冲层分区新型SJ-LDMOS结构.新结构利用电场调制效应将分区缓冲层产生的电场峰引入超结(super junction)表面而优化了SJ-LDMOS的表面电场分布,缓解了横向LDMOS器件由于受纵向电场影响使横向电场分布不均匀、横向单位耐压量低的问题.利用仿真分析软件ISE分析表明,优化条件下,当缓冲层分区为3时,提出的缓冲层分区SJ-LDMOS表面电场最优,击穿电压达到饱和时较一般LDMOS结构提高了50%左右,较缓冲层SJ-LDMOS结构提高了32%左右,横向单位耐压量达到18.48 V/μm.击穿电压为382 V的缓冲层分区SJ-LDMOS,比导通电阻为25.6 mΩ·cm2,突破了一般LDMOS击穿电压为254 V时比导通电阻为71.8 mΩ·cm2的极限关系.     

Improved performance of MoS2 FET by in situ NH3 doping in ALD Al2O3 dielectric

Since defects such as traps and oxygen vacancies exist in dielectrics, it is difficult to fabricate a high-performance MoS$_{2}$ field-effect transistor (FET) using atomic layer deposition (ALD) Al$_{2}$O$_{3}$ as the gate dielectric layer. In this paper, NH$_{3}$ in situ doping, a process treatment approach during ALD growth of Al$_{2}$O$_{3}$, is used to decrease these defects for better device characteristics. MoS$_{2}$ FET has been well fabricated with this technique and the effect of different NH$_{3}$ in situ doping sequences in the growth cycle has been investigated in detail. Compared with counterparts, those devices with NH$_{3}$ in situ doping demonstrate obvious performance enhancements: $I_{\rm on}/I_{\rm off}$ is improved by one order of magnitude, from $1.33\times 10^{5}$ to $3.56\times 10^{6}$, the threshold voltage shifts from $-0.74 $ V to $-0.12$ V and a small subthreshold swing of 105 mV/dec is achieved. The improved MoS$_{2}$ FET performance is attributed to nitrogen doping by the introduction of NH$_{3}$ during the Al$_{2}$O$_{3}$ ALD growth process, which leads to a reduction in the surface roughness of the dielectric layer and the repair of oxygen vacancies in the Al$_{2}$O$_{3}$ layer. Furthermore, the MoS$_{2}$ FET processed by in situ NH$_{3}$ doping after the Al and O precursor filling cycles demonstrates the best performance; this may be because the final NH$_{3}$ doping after film growth restores more oxygen vacancies to screen more charge scattering in the MoS$_{2}$ channel. The reported method provides a promising way to reduce charge scattering in carrier transport for high-performance MoS$_{2 }$ devices.     

Electron field emission from single-walled carbon nanotube nonwoven

Field emission from single-walled carbon nanotube (SWNT) nonwoven has been investigated under high vacuum with different vacuum gaps. A low turn-on electric field of 1.05\,V/$\mu $m is required to reach an emission current density of 10 $\mu $A/cm$^{2}$. An emission current density of 10 mA/cm$^{2}$ is obtained at an operating electric field of 1.88\,V/$\mu $m. No current saturation is found even at an emission current of 5\,mA. With the vacuum gap increasing from 1 to 10 mm, the turn-on field decreases monotonically from 1.21 to 0.68\,V/$\mu $m, while the field amplification is augmented. The good field-emission behaviour is ascribed to the combined effects of the intrinsic field emission of SWNT and the waved topography of the nonwoven.     

New CMOS compatible super junction LDMOST with n-type buried layer

A new super-junction lateral double diffused MOSFET (LDMOST) structure is designed with n-type charge compensation layer embedded in the p$^{ - }$-substrate near the drain to suppress substrate-assisted depletion effect that results from the compensating charges imbalance between the pillars in the n-type buried layer. A high electric field peak is introduced in the surface by the pn junction between the p$^{ - }$-substrate and n-type buried layer, which given rise to a more uniform surface electric field distribution by modulation effect. The effect of reduced bulk field (REBULF) is introduced to improve the vertical breakdown voltage by reducing the high bulk electric field around the drain. The new structure features high breakdown voltage, low on-resistance and charges balance in the drift region due to n-type buried layer.     

Parameter extraction for a Ti/4H-SiC Schottky diode

Based on the MIS model, a simple method to extract parameters of SiC Schottky diodes is presented using the $I$-$V$ characteristics. The interface oxide capacitance $C_\i$ is extracted for the first time, as far as we know. Parameters of 4H-SiC Schottky diodes fabricated for testing in this paper are: the ideality factor $n$, the series resistance $R_{\rm s}$, the zero-field barrier height $\phi_{\rm B0}$, the interface state density $D_{\rm it}$, the interface oxide capacitance $C_\i$ and the neutral level of interface states $\phi_0$.