Low power options for 32 nm always-on SRAM architecture

The SRAM 6T bit-cell suffers many limitations in advanced technology nodes among which variability effects. Various alternatives have been experimented and the paper focuses on the 5T-Portless bit-cell. Read and write operations are operated by varying voltage conditions. Literature regarding 32 nm CMOS for Portless SRAM has been reviewed and improvements are presented. The bit-cells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bit-cell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption beneficial to always-on memories. The paper presents different existing solutions to limit the power consumption and their limitations in thin CMOS technologies. The portless bit-cell is presented as a low power architecture alternative to 6T-SRAM. A matrix test-chip is currently under fabrication in bulk CMOS 32 nm.     

DATA BYPASSING ARCHITECTURE AND CIRCUIT DESIGN FOR 32-BIT DIGITAL SIGNAL PROCESSOR

This paper presents a design method of ByPassing Unit（BPU） in 32-bit Digital Signal Processor（DSP）-MD32. MD32 is realized in 0.18 μm technology, 1.8V and 200 MHz working clock. It focuses on the Reduced Instruction Set Computer（RISC） architecture and DSP computation capability thoroughly, extends DSP with various addressing modes in a customized DSP pipeline stage architecture. The paper also discusses the architecture and circuit design of bypassing logic to fit MD32 architecture. The parallel execution of BPU with instruction decode in architecture level is applied to reduce time delay. The optimization of circuit that serial select with priority is analyzed in detail, and the result shows that about half of time delay is reduced after this optimization. Examples show that BPU is useful for improving the DSP＇s performance. The forwarding logic in MD32 realizes 8 data channels feedback and meets the working clock limit.     

Design and analysis of a compact fast parallel multiplier for high speed DSP applications using novel partial product generator and 4 : 2 compressor

Parallel multiplier is one of the most important building blocks in all the DSP processors, which needs faster computations. To reduce the total transistor count in a multiplier we have proposed two new approaches. The first approach is using a 26 transistor booth encoder and a 8-transistor/partial-product booth selector to generate partial products. The second approach proposes a new circuit for 4 : 2 compressors. The booth encoder and booth selector reported here are the smallest in transistor count, but comparable to the best delay with less power consumption. This paper describes a comparison of a compact 16 × 16 parallel multiplier using the new circuit components. This shows a transistor count advantage of 27% and 52% in partial product generation and partial product accumulation, respectively.     

Low power multipliers based on new hybrid full adders

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8×8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.     

Low energy and area efficient quaternary multiplier with carbon nanotube field effect transistors

In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.     

Low power high output impedance high bandwidth QFGMOS current mirror

Current mirror is a basic block of any mixed-signal circuit for example in an analog-to-digital converter. Its precise performance is the key requirement for analog circuits where offset is a measure issue. The key parameter which defines the performance of current mirror is its input/output impedance, input swing, and bandwidth. In this paper, a low power design of current mirror using quasi-floating gate MOS transistor is presented. The proposed current mirror boosts its output impedance in range of giga-ohm through use of regulated cascode structure followed by super-cascode. Another improvement is done in reduced input compliance voltage limits with the help of level shifter. The proposed current mirror operates well for input current range 0–700 $\mathrm{\mu }A$ with an input and output impedance of 160 $\Omega$ and 8.55 $\mathrm{G}\Omega$ respectively and high bandwidth of 4.05 $\mathrm{GHz}$. The total power consumption of the proposed current mirror is about 0.84 mW. The low power consumption with enhanced output impedance and bandwidth suits proposed current mirror for various high-speed analog designs. Performance of the presented current mirror circuit is verified using HSpice simulations on 0.18 $\mathrm{\mu }m$ mixed-mode twill-well technology at a supply voltage of ±0.5 V.     

磁盘阵列中高速并行RS译码算法研究

该文在总结研究 RS译码的基础上,给出了一种适合并行方式进行高速 RS译码的方法,该方法对于高速数据磁盘阵列录取系统、高速数据通信系统的纠错译码效果显著,已成功地应用到磁盘阵列高速数据录取系统中。     

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like ‘Urdhva-tiryakbyham’ (UT) and ‘Nikhilam Navatascaramam Dasatah’ (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90 nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only ∼42.13 ns while the power consumption of the same was ∼58.82 mW for a layout area of ∼6 mm². Improvement in speed was found to be ∼33% and ∼24% while corresponding reduction of power consumption in ∼34.48% and ∼24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.     

Low power test architecture for dynamic read destructive fault detection in SRAM

Dynamic Read Destructive Fault (dRDF) is the outcome of resistive open defects in the core cells of static random-access memories (SRAMs). The sensitisation of dRDF involves either performing multiple read operations or creation of number of read equivalent stress (RES), on the core cell under test. Though the creation of RES is preferred over the performing multiple read operation on the core cell, cell dissipates more power during RES than during the read or write operation. This paper focuses on the reduction in power dissipation by optimisation of number of RESs, which are required to sensitise the dRDF during test mode of operation of SRAM. The novel pre-charge architecture has been proposed in order to reduce the power dissipation by limiting the number of RESs to an optimised number of two. The proposed low power architecture is simulated and analysed which shows reduction in power dissipation by reducing the number of RESs up to 18.18%.     

面向椭圆曲线密码的处理器并行体系结构研究与设计

在研究椭圆曲线密码算法的处理特征以及有限域层上的并行调度算法基础上,采用指令级并行和数据级并行方法,提出了面向椭圆曲线密码的并行处理器体系结构模型,并就模型的存储结构进行了分析。基于该模型实现了一款验证原型,在FPGA上成功进行了验证测试并在0.18μm CMOS工艺标准单元库下进行逻辑综合以及布局布线。实验证明提出的并行处理器体系结构既能保证椭圆曲线密码算法应用的灵活性,又能够达到较高的性能。     

一种高精度大功率电镀电源设计

针对传统电镀电源体积大、实现方式复杂以及输出纹波大的特点,提出了一种新型的DC/DC变换器,采用双闭环PWM实时控制方式,具有恒电流和恒电压两种工作方式。用该方法设计了一组9.6 kW电源模块,实验表明,电源输出纹波系数小于1%,效率达到90%。     

智能配电系统架构分析及技术的研究

作为电网中的重要组成部分,智能配电系统会对电网运行效率、运行安全等方面产生直接影响.为了有效控制电网故障的发生概率,应该注重智能配电系统性能的提升.本文从智能配电系统的概念入手,对智能配电系统架构和技术进行分析和研究.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

低轨卫星与5G-R融合网络架构设计

由于地面网络覆盖不均匀,信号质量不够稳定,无法实现铁路交通网络的全程、快速、实时监测,阻碍了我国铁路交通网络的快速发展。同时,低轨卫星通信与地面5G的融合成为热点,二者的融合能够使卫星网络作为地面网络的有效补充。当前星地融合较少用于5G-R技术场景中。本文梳理了铁路卫星通信以及星地融合网络的研究现状与发展趋势;分析了铁路通信系统中各业务的通信需求。在此基础上,提出低轨卫星与5G-R融合网络架构。在弥补铁路通信网络覆盖盲区的同时,提供大容量的信息回传,有效保障铁路交通的安全运行,实现铁路交通的信息化、智能化管理。     

Implementation of low power adder design and analysis based on power reduction technique

This paper presents improved design of low power adder and analysis based on power reduction technique. Using example of adder and multiplier, low leakage power CMOS digital circuit is verified by respective benchmark suite for each example and compared with conventional design of adder and multiplier.Using various supply voltages and fault coverage as parameters, reduction in power was measured. Simulation result and validation by example foresee implementation of proposed design as an essential part of high performance circuit design.The proposed technique offer power reduction up to 20.2% and fault coverage of 99.65%.     

40Gbit／s高速并行12信道光接收模块的研制

研究并制作了12信道并行光接收模块,单信道传输速率大于等于3．318Gbit／s,12信道并行总传输速率为40Gbit／s。模块采用工作波长在850nm的高速PIN型光电探测器（PD）列阵作为光接收器件,PD列阵与接收电路芯片直接用Au丝压焊连接,输入光信号直接由12信道的光纤阵列耦合进入PD列阵中。对光接收模块进行眼...     

一种低功耗低温度系数基准电压源的设计

基于0.35μm CMOS工艺,设计一种不带电阻的低功耗基准电压源,该基准源工作电压范围1.2 V~3.6 V.在3.6 V和室温时测量最大的电源电流为130 nA.在-20℃~100℃温度范围内,该基准电压温度系数为7.5×10-6/℃.在1.2 V~3.6 V电源电压范围内,线灵敏度为40×10-6/V,且在100 Hz时电源抑制比为-50 dB.该基准电压源适合在一些例如移动设备、植入式医疗设备和智能传感器网络等节能集成电路上应用.