多通道时域交织逐次逼近型模数转换器通道失配建模

时域交织ADC由多个独立的ADC构成,这种并行处理数据的方式可以达到很高的采样率。子通道采用SAR ADC可实现低功耗并保持很好的线性度。但是,这种结构受到三种失配的影响：失调失配,增益失配和采样时刻偏差。本文从频域分析出发,重点研究了在通道数目较多的情况下失配对TI SAR ADC性能的影响,此外,推导得出M通道交织ADC的DNL和INL的均方根值是单通道ADC均方根值的1/√M。最后通过Matlab仿真验证了推导出的公式。这些公式可以为设计TI ADC时确定失配范围提供参考,并为提出校准算法提供思路。     

1-V电源65nm GP CMOS工艺下一款十位80MS/s 1.6mW逐次逼近型模数转换器

This paper presents a 10-bit 80-MS/s successive approximation register(SAR) analog-to-digital converter (ADC) suitable for integration in a system on a chip(SoC).By using the top-plate-sample switching scheme and a split capacitive array structure,the total capacitance is dramatically reduced which leads to low power and high speed.Since the split structure makes the capacitive array highly sensitive to parasitic capacitance,a three-row layout method is applied to the layout design.To overcome the charge leakage in the nanometer process,a special input stage is proposed in the comparator.As 80 MS/s sampling rate for a 10-bit SAR ADC results in around 1 GHz logic control clock,and a tunable clock generator is implemented.The prototype was fabricated in 65 nm 1P9M (one-poly-nine-metal) GP(general purpose) CMOS technology.Measurement results show a peak signal-to-noise and distortion ratio(SINAD) of 48.3 dB and 1.6 mW total power consumption with a figure of merit(FOM) of 94.8 fJ/conversion-step.     

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

正A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step.     

一种基于时域比较器高SFDR的6-bit 20-MS/s 逐次逼近模数转换器

This paper presents a 6-bit 20-MS/s high spurious-free dynamic range(SFDR) and low power successive approximation register analog to digital converter(SAR ADC) for the radio-frequency(RF) transceiver frontend, especially for wireless sensor network(WSN) applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits(ENOB) of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity(DNL) is less than 0.83 LSB and the integral nonlinearity(INL) is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm~2.     

8位12MS/s带片上参考电压的异步逐次逼近模数转换器

This paper proposes an 8 bit asynchronous successive approximation register ADC for wireless transceivers.A split capacitor DAC is used to reduce power and area consumption and the value of the split capacitor is calculated theoretically to ensure linearity.Asynchronous control logic is proposed to eliminate the high internal clocks and significantly speeds up the successive approximation algorithm.An on-chip reference with a fully integrated buffer and decoupling capacitor is adopted for avoiding an extra pin for the off-chip reference. The prototype,fabricated in UMC 0.18μm CMOS technology,achieves an effective number of bits of 7.64 bits at a sampling frequency of 12 MS/s.The total power consumption is 0.918 mW for a 1.8 V supply,while the onchip reference consumes 53%of the total power.It achieves a figure of merit of 180 fJ/conv-step,excluding the reference’s power consumption.     

一种带校准的1.8V 1.1MS/s 96.1dB-SFDR的逐次逼近模数转换器

A power efficient 96.1 dB-SFDR successive approximation register(SAR) analog-to-digital converter (ADC) with digital calibration aimed at capacitor mismatch is presented.The prototype is fabricated in a 0.18μm CMOS.The charge redistribution(CR) design and an extra△∑modulator for capacitance measurement are employed. With a 1.1 MS/s sampling rate,the ADC achieves 70.8 dB SNDR and the power consumption is 2.1 mW.     

一种基于电阻型数模转换器每级输出3位的6-bit 410-MS/s单通道异步逐次逼近模数转换器

该设计采用SMIC 65-nm CMOS工艺,实现了一款可应用于超宽带通信领域的单通道低功耗6位410-MS/s异步逐次逼近模数转换器(SAR ADC)。通过采用电阻型数模转换器、每级输出3位数字码字结构,以及改进的异步控制逻辑,该ADC在370-MS/s采样率时,无杂散动态范围(SFDR)达到41.95-dB,信号噪声失真比(SNDR)达到28.52-dB。在采样率为410MS/s时,该设计仍能达到40.71-dB的SFDR和30.02-dB的SNDR。通过动态比较器的使用,实现了低功耗设计。测试结果表明,在410-MS/s采样率下,电路总功耗为2.03mW,对应的品质因子(FOM)为189.17fJ/step。     

一种带12位3.2 MS/s 逐次逼近型模数转换器的电源线通信模拟前端电路

This paper presents an analog front end for a power line communication system,including a 12-bit3.2-MS/s energy-efficient successive approximation register analog-to-digital converter,a positive feedback programmable gain amplifier,a 9.8 ppm/°C bandgap reference and on-chip low-output voltage regulators.A two segment capacitive array structure(6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements.Implemented in the GSMC 0.13 m 1.5 V/12 V dual-gate 4P6 M e-flash process,the analog front end occupies an area of 0.457 mm2 and consumes power of18.8 m W,in which 1.1 m W cost by the SAR ADC.Measured at 500 k Hz input,the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 d B and 60.60 d B respectively,achieving a figure of merit of 350 f J/conversion-step.     

一种用于Pipeline ADC的高线性度栅压自举开关

在流水线模数转换器(Pipeline ADC)电路中,栅压自举开关中的非线性电容会对开关管的导通电阻产生直接的影响,导致采样非线性。设计了一种三路径的高线性度栅压自举开关,采用三个自举电容,分别构成两条主路径和一条辅助路径,使得输入信号在通过两条主路径传输到开关管栅端时加快栅端电压的建立,同时利用辅助路径驱动非线性电容,减少电路中非线性电容对采样电路线性度的影响,从而增强信号驱动能力,提高整体电路的精度。本文设计的栅压自举开关应用于14 bit 500 MHz流水线ADC的采样保持电路中。采用TSMC 28 nm CMOS工艺进行电路设计。仿真结果表明,在输入频率为249 MHz,采样频率为500 MHz的条件下,该栅压自举开关的信噪比(SNDR)达到92.85 dB,无杂散动态范围(SFDR)达到110.98 dB。     

一个高线性13位流水线CMOS A/D转换器

介绍了一个采用多种电路设计技术来实现高线性13位流水线A/D转换器.这些设计技术包括采用无源电容误差平均来校准电容失配误差、增益增强(gain-boosting)运放来降低有限增益误差和增益非线性,自举(bootstrapping)开关来减小开关导通电阻的非线性以及抗干扰设计来减弱来自数字供电的噪声.电路采用0.18μm CMOS工艺实现,包括焊盘在内的面积为3.2mm2.在2.5MHz采样时钟和2.4MHz输入信号下测试,得到的微分非线性为-0.18/0.15LSB,积分非线性为-0.35/0.5LSB,信号与噪声加失真比(SNDR)为75.7dB,无杂散动态范围(SFDR)为90.5dBc;在5MHz采样时钟和2.4MHz输入信号下测试,得到的SNDR和SFDR分别为73.7dB和83.9dBc.所有测试均在2.7V电源下进行,对应于采样率为2.5MS/s和5Ms/s的功耗(包括焊盘驱动电路)分别为21mW和34mW.     

On the design of high-speed energy-efficient successive-approximation logic for asynchronous SAR ADCs

This paper analyzes the power consumption and delay mechanisms of the successive-approximation (SA) logic of a typical asynchronous SAR ADC, and provides strategies to reduce both of them. Following these strategies, a unique direct-pass SA logic is proposed based on a full-swing once-triggered DFF and a self-locking tri-state gate. The unnecessary internal switching power of a typical TSPC DFF, which is commonly used in the SA logic, is avoided. The delay of the ready detector as well as the sequencer is removed from the critical path. A prototype SAR ADC based on the proposed SA logic is fabricated in 130 nm CMOS. It achieves a peak SNDR of 56.3 dB at 1.2 V supply and 65 MS/s sampling rate, and has a total power consumption of 555 μ W, while the digital part consumes only 203 μ W.     

一个11位、采样率22MS/s、0.6毫瓦采用寄生电容补偿技术的逐次逼近型模数转换器

本文介绍了一个11位22MS/s采样率功耗为0.6毫瓦的逐次逼进型模数转换器,采用了中芯国际65nm低漏电工艺,工作电压为1.2V。采用了桥接电容阵列来降低总电容值和芯片面积。但是桥接电容阵列的低位寄生电容会影响模数转换器的线性度并且难于校正。本文提出了一种寄生电容补偿技术避免使用复杂的校正电路来消除低位寄生电容带来的不利影响。本文的数字逻辑采用了动态电路来降低功耗并且缩短关键路径的延迟时间。芯片面积为300微米×200微米,测试结果表明采样率为22-MS/s ,在1.2V的工作电压下功耗为0.6毫瓦,输入信号为低频信号时信号噪声失真比为59.3dB,无杂散动态范围为72.2 dB。品质因数为36.4fJ/conversion-step。     

一种三阶混合结构的噪声整形SAR ADC北大核心

设计了一种三阶噪声整形逐次逼近模数转换器。该转换器采用由二阶误差反馈结构和一阶级联积分器前馈结构组成的混合噪声整形结构，通过该混合结构来控制反馈余量并提升噪声传输函数的阶数，通过基于共模的开关切换方式优化了比较器动态失调电压，实现了三阶噪声传输函数。该电路基于0.35μm CMOS工艺进行设计仿真。使用3.3 V电源电压进行供电，在2 MS/s采样频率以及8倍过采样率下，功耗为1.87 mW,实现了87.93 dB的SNDR,有效位数(ENOB)为14.3 bit,在传统8位SAR ADC的基础上提升了有效位数6.3 bit。     

Energy-efficient CMOS delay line with self-supply modulation for low-power SAR ADCs

ABSTRACT

A new digital delay line based on the inverter chain is proposed. The proposed new method of connection of the inverters allows much longer delay times to be achieved for the same number of transistors, the same amount of power to be consumed as for conventional connection of inverters. Simulation results using a 65 nm CMOS design kit from ST Microelectronics are provided. An application example of the proposed delay line is provided for low-power, low-speed successive approximation register (SAR) analogue-to-digital converters (ADC).     

一种8-b 180KSPS的带有新颖的时域比较器且有效位数7.97的差分逐次逼近模数转换器

This paper presents a differential successive approximation register analog-to-digital converter (SAR ADC) with a novel time-domain comparator design for wireless sensor networks. The prototype chip has been implemented in the UMC 0.18-μ m 1P6M CMOS process. The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz. With the Nyquist input frequency, 68.49-dB SFDR, 7.97-ENOB is achieved. A simple quadrate layout is adopted to ease the routing complexity of the common-centroid symmetry layout. The ADC maintains a maximum differential nonlinearity of less than 0.08 LSB and integral nonlinearity less than 0.34 LSB by this type of layout.     

An 8-bit 180-kS/s differential SAR ADC with a time-domain comparator and 7.97-ENOB

This paper presents a differential successive approximation register analog-to-digital converter(SAR ADC) with a novel time-domain comparator design for wireless sensor networks.The prototype chip has been implemented in the UMC 0.18-μm 1P6M CMOS process.The proposed ADC achieves a peak ENOB of 7.98 at an input frequency of 39.7 kHz and sampling rate of 180 kHz.With the Nyquist input frequency,68.49-dB SFDR,7.97-ENOB is achieved.A simple quadrate layout is adopted to ease the routing complexity of the co...     

High-linear,energy-efficient and area-efficient switching algorithm for high-speed SAR ADCs

Decreasing the size of DAC capacitors is a solution to achieve high-speed and low-power successive-approximation register analog-to-digital converters (SAR ADCs). But decreasing the size of capacitors directly effects the linearity performance of converter. In this paper, the effect of capacitor mismatch on linearity performance of charge redistribution SAR ADCs is studied. According to the achieved results from this investigation, a new tri-level switching algorithm is proposed to reduce the matching requirement for capacitors in SAR ADCs. The integral non-linearity (INL) and the differential non-linearity (DNL) of the proposed scheme are reduced by factor of two over the conventional SAR ADC which is the lowest compared to the previous schemes. In addition, the switching energy of the proposed scheme is reduced by 98.02% as compared with the conventional architecture which is the most energy-efficient algorithms in comparison with the previous algorithms, too. To evaluate the proposed method an 8-bit 50 MS/s SAR ADC is designed in 0.18 um CMOS process technology. According to the obtained simulation results, the designed ADC digitizes a 25-MHz input with 48.16 dB SNDR while consuming about 589 μW from a 1.2-V supply.     

11有效位数，精度可编程且非校正的时间模式逐次逼近模数转换器

设计了一种10或者12位的可编程差分逐次逼近模数转换器,用于桥梁应力监测系统。该模数转换器采用了一种新颖的时域比较器,且提出了几种提高时域比较器精度的技术。该芯片在UMC 0.18um工艺上实现。当模数转换器工作于12位模式100K采样率时,输入47.7kHz正弦波时, 有效位数为11,无杂散动态范围为77.48dB, 最大微分非线性为0.2/-0.74LSB,最大积分非线性为 1.27/-0.97LSB,总功耗为558uW。     

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer(TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.     

An ll-bit 22-MS/s 0.6 mW SAR ADC with parasitic capacitance compensation

Abstract： This paper presents an l 1-bit 22-MS/s 0.6-mW successive approximation register （SAR） analog-to- digital converter （ADC） using SMIC 65-nm low leakage （LL） CMOS technology with a 1.2 V supply voltage. To reduce the total capacitance and core area the split capacitor architecture is adopted. But in high resolution ADCs the parasitic capacitance in the LSB-side would decrease the linearity of the ADC and it is hard to calibrate. This paper proposes a parasitic capacitance compensation technique to cancel the effect with no calibration circuits. Moreover, dynamic circuits are used to minimize the switching power of the digital logic and also can reduce the latency time. The prototype chip realized an 11-bit SAR ADC fabricated in SMIC 65-nm CMOS technology with a core area of 300 × 200 μm2. It shows a sampling rate of 22 MS/s and low power dissipation of 0.6 mW at a 1.2 V supply voltage. At low input frequency the signal-to-noise-and-distortion ratio （SNDR） is 59.3 dB and the spurious-free dynamic range is 72.2 dB. The peak figure-of-merit is 36.4 fJ/conversion-step.