基于DSP环境下C语言的编程优化

DSP作为一项新型技术,具有实时、准时等优势,在此类系统中,能够运用合理的片内结构,实现对数字信号的专门性处理,提高信号处理有效性.但随着DSP应用范围愈发广泛,汇编语言程序可读性、可移植性等缺陷逐渐暴露出来,且汇编语言是非结构化语言,对于大型的结构化程序设计难以胜任,要求我们采用更为高级的语言完成该项工作.相比较现有汇编语言,C语言无疑是最为高效和灵活的,如何在DSP环境下实现对C语言编程优化受到了广泛关注.文章将从DSP的特点出发,深入分析在DSP环境下C语言编程的优化措施,希望对DSP平台完善提供参考.     

DSP开发中C编程的优化考虑

由于DSP的特殊结构，使得在DSP开发中C编译器的效率较低，编译产生的汇编代码有较大冗余，难以使DSP的运算能力发挥至最大。本文旨在实现代码的高效和得到运算速度的改善，从仿真环境和DSP开发环境两个方面进行了一些分析。     

DSP仿真环境下ELASH的编程以及DSP引导

本文详细介绍了一种在DSP仿真环境下对FLASH的编程方法，同时根据DSP的boot机制，介绍了从FLASH进行boot的途径，为开发利用FLASH提供了思路。     

用高级语言设置TMS320DSP中断

本文描述了设置数字信号处理器中断应注意的问题和用C设置中断的几种方法。     

用高级语言实现DSP中断编程

中断处理是大多数DSP应用系统中不可缺少的一个重要环节。文中详细介绍了一种用C语言实现DSP中断的方法，该方法仅使用外围支持库文件(dev6x.lib)中的函数及宏定义即可简单地完成中断服务程序的设置。同时介绍了中断的一些基本概念以及中断控制寄存器的设置方法，并给出了中断服务程序设置例程。     

H.264编解码器在C6416 DSP上的实现与优化

H.264是由ITU-T和ISO联合制定的新一代视频编码标准,有着码率低,质量高的特点.C64x系列DSP是目前TI公司推出的性能最高的定点DSP,NVDK(Network Video Development Kit)是其很好的仿真平台.本文介绍了H.264基于TIC6416DSP的优化与实现方法,通过仿真实验,编解码器在Qcif格式下达到实时编解码效果,能够满足实时通信要求.本文介绍了H.264在DSP上实现和优化的手段,最后给出实验结果.     

在高级语言环境下实现快速DSP功能

本文提出了在高级语言环境下实现快速DSP（DigitalSignalProcessing，简记DSP）功能的方案构想、实现途径，为用户更方便地使用专用DSP功能提供了可能。     

用ANSI C语言开发DSP程序的原理和方法

用ANSI C高级语言进行DSP系列的开发是DSP发展的重要方向，以TMS320C54X为例，对使用ANSI C编译器开发程序进行了介绍。     

数字信号处理器第二讲实时DSP系统设计开发流程和DSP处理器开发工具简介

在设计需求规范,确定设计目标时,其实要解决二个方面的问题：即信号处理方面和非信号处理的问题。信号处理的问题包括：输入、输出结果特性的分析,DSP算法的确定,以及按要求对确定的性能指标在通用机上用高级语言编程仿真。非信号处理问题包括：应用环境、设备的可靠性指标,设备的可维护性,功耗、体积重量、成本、性能价格比等项目。     

用C语言实现高效嵌入式系统编程

用高级语言C进行嵌入式系统的编程有着汇编语言编程不可比拟的优势，并已成为未来必然的发展趋势，本根据作的实际开发经验，以KEILC51为开发工具，首先介绍高级语言C的编程优势，然后介绍C51与标准C语言的主要不同点，介绍用高级语言C进行嵌入式系统编程的特点，介绍如何快速编出规范，高效而又精简的C语言程序，以及如何对程序进行优化。     

DSP环境下C代码的手工汇编优化

由于DSP器件的特殊结构,使得该平台上C编译器的效率较低,编译生成的汇编代码含有大量冗余,无法充分发挥DSP强大的运算能力,因而对C语言程序进行手工汇编优化就成为DSP软件开发和移植中常用的方法。TMS320C5410是TI推出的一款16位定点DSP芯片,结合在该芯片上优化实现G.729语音编码压缩算法的经验,详细探讨了手工汇编优化过程中使用的优化策略以及其他注意事项。     

由求解自然对数算法分析DSP中的优化策略

以一个具体的例子:自然对数运算求解展开来解释了DSP中的优化策略。DSP中的优化可分为三个部分:算法级的优化、定点C级的优化和汇编级的优化。三部分的优化在提高DSP的性能和效率上都是不可或缺的。同时提供了自然对数运算的算法、定点C流程和汇编源代码供参考。     

实时操作系统DSP/BIOS在DSP开发中的应用

本文介绍了实时操作系统DSP/BIOS在DSP开发中的应用。首先简述了DSP应用的一般模型,并说明了实时操作系统在DSP外设管理,实时性能分析,程序总体流程控制中的应用。     

面向DSP应用的可重构计算

DSP应用的特点是计算密集并适合并行处理,传统的可编程处理器与ASIC在性能和灵活性上各有优劣.因此出现了一种新的计算模式-可重构计算.由于它能将效率和灵活性很好地结合在一起,故正得到广泛的关注和研究.本文在介绍可重构计算的概念和分类的基础上,着重讨论了一些主流的可重构计算系统,分析了各类系统应用于DSP的特点,对可重构计算在计算模型,编译器,映射技术以及开发环境等方面的现状和趋势进行了探讨,并给出了自己的思考.     

一种实用的DSP程序代码转换技术

拥有强大控制功能的ARM+高效快速实时计算能力的DSP双核结构,在电力系统的保护和监控中发挥着重要的作用。在对DSP 核进行开发的过程中,需要解决DSP 应用程序代码格式转换的问题。文章详细介绍了一种简单易行,实用性强的转换技术,并通过实际平台的测试证明其正确性。     

An Efficient Code Generation Algorithm for Non-orthogonal DSP Architecture

To meet strict speed and power requirements for embedded applications, many high-end digital Signal Processors (DSPs) commonly employ non-orthogonal architectures that are typically characterized by irregular data paths, heterogeneous registers, and multiple memory banks. Obviously to harvest the benefits provided by this non-orthogonal architecture sufficient compiler support is necessary and important. However, the complexity of such architectures presents a great challenge to compiler design and the usual compilation techniques for general-purpose CPUs do not adapt well to the irregularity of DSP. The entire code generation process must include the following phases: intermediate representation, code compaction, instruction scheduling, memory bank assignment (or variable partition), and register/accumulator assignment. Much related research only considers some phases, which is inadequate. In this paper, we present an effective code generation algorithm named Rotation Scheduling with Spill Codes Predicting (RSSP) to maximally exploit the benefits of non-orthogonal architectures. It contains six parts that cover almost the entire phases of the code generation process. As well as introducing the detailed principles and algorithms of the proposed RSSP, we use an analytic model to evaluate its preliminary performance. Evaluation results clearly demonstrate the effectiveness of the proposed method. Furthermore, we also present some preliminary ideas to generalize RSSP, which can make it more practicable and suit various DSPs with similar architectural features.

DSP基条码扫描器

本文介绍了一种基于DSP技术的二维条码扫描器.     

Implementation of a Wireless Multimedia DSP Chip for Mobile Applications

This paper presents the implementation of a wireless multimedia DSP chip for mobile applications. The implemented DSP chip supports communication instructions for Viterbi, timing synchronization, etc. as well as multimedia instructions. The DSP can handle variable length data and perform four MACs in a cycle. The proposed DSP employs parallel processing techniques, such as SIMD, vector processing, DSP schemes and adopts low power features for wireless applications. The implemented DSP chip includes test circuits and various peripherals, such as DMA, bus arbitration, timer, etc. This chip has been modeled by Verilog HDL and implemented using the 0.35 m HCB60 library. The total gate count excluding memory is about 170,000 gates and the clock frequency is 100 MHz.Junghoo Lee received the B.S. degree in electronic engineering from Ajou University, Suwon, Korea in 2002. He is currently working toward the Ph.D. degree with School of Electrical and Computer Engineering, Ajou University. His main research interests include SOC design and application-specific DSP chip design.Myung H. Sunwoo received the B.S. degree in electronic engineering from the Sogang University in 1980, the M.S. degree in electrical and electronics from the Korea Advanced Institute of Science and Technology in 1982, and the Ph.D. degree in electrical and computer engineering from the University of Texas at Austin in 1990.He worked for Electronics and Telecommunications Research Institute (ETRI) in Daejeon, Korea from 1982 to 1985 and Digital Signal Processor Operations, Motorola, Austin, TX from 1990 to 1992. Since 1992, he has been a Professor with the School of Electrical and Computer Engineering, Ajou University in Suwon, Korea. In 2000, he was a Visiting Professor in the Department of Electrical and Computer Engineering, the University of California, Davis, CA. He is the Director of the National Research Laboratory sponsored by the Ministry of Science and Technology. His research interests include VLSI architectures, SOC design for multimedia and communications, and application-specific DSP architectures.Dr. Sunwoo has published more than 120 papers in international transactions/journals and conferences and also has 28 patents including five U.S. patents. He served as a Technical Program Chair of the IEEE Workshop on Signal Processing Systems (SIPS) in 2003 and a member of the technical program committee of various international conferences. He has received a number of research awards from the Ministry of Commerce, Industry and Energy, Samsung Electronics, and professional foundations. He served as an Associate Editor for the IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2002–2003) and as a Guest Editor for the Journal of VLSI Signal Processing (Kluwer, 2004). Currently, He is a Senior Member of IEEE and a Chair of the IEEE CAS Society of the Seoul Chapter.     

基于DSP Builder的巴克码检出设计及FPGA实现

巴克码是最常用的帧同步码组。为了实现巴克码组的有效检出,利用DSP Builder设计了一种新的13位巴克码识别器电路。在Matlab/Simulink中对设计的电路进行了纯数字仿真,然后将设计的系统载入到FPGA芯片中,运用硬件在回路仿真技术进行半实物仿真。结果表明,基于DSP Builder设计的巴克码检出电路简单易行、稳定可靠,达到了预期的要求。     

WCDMA标准中Turbo码译码的DSP实现

介绍了Motorola公司新一代定点数字信号处理芯片MSC8101的特点,以及Turbo码译码在MSC8101上的实现技术。