Comparison of latchup immunity for silicided source/drain at different n implant energy

The effect of titanium disilicide (TiSi₂) on latchup immunity for different n⁺ source/drain (s/d) junction depth is investigated. Highly latchup immune 0.25 μm CMOS devices have been fabricated with a 50 Ågate oxide, retrograde twin-well and titanium silicided shallow s/d. The trigger current (I_trig) more than doubled from 14 to 32 mA, while the current gain of the npn parasitic BJT (β) is reduced from 4.9 to 2.5. These improvements are observed when comparing between non-silicided and silicided s/d with shallow junction (at 30 keV). However, when the s/d junction is deep (at 40 keV), the improvement in latchup immunity of silicided s/d over non-silicided s/d decreases. In addition, silicided wafers with shallow junction are more latchup immune than those with deep junction. The above observations are attributed to the reduction of the emitter width and the dopant consumption during TiSi₂ formation, enhanced hole injection due to thinner interfacial oxide, and larger contact area of the silicide and silicon (Si).     

Source/drain contact resistance of silicided thin-film SOI MOSFET's

We developed a source/drain contact (S/D) resistance model for silicided thin-film SOI MOSFET's, and analyzed its dependence on device parameters considering the variation in the thickness of the silicide and residual SOI layers due to silicidation. The S/D resistance is insensitive to the silicide thickness over a wide range of thicknesses; however, it increases significantly when the silicide thickness is less than one hundredth of initial SOI thickness, and when almost all the SOI layer is silicided. To obtain a low S/D resistance, the specific contact resistance must be reduced, that is, the doping concentration at the silicide-SOI interface must be more than 10²⁰ cm^-3     

The leakage current improvement in an ultrashallow junction NMOSwith Co silicided source and drain

The leakage current characteristics of the cobalt silicided NMOS transistors with a junction depth of 800 Å have been studied. In order to minimize the junction leakage current, the thickness of the CoSi₂ layer should he controlled under 300 Å and the Si surface damage induced by the gate spacer etch should be minimized. The post furnace annealing after the second silicidation by the rapid thermal annealing (RTA) process also affected the leakage current characteristics. The gate induced drain leakage (GIDL) current was not affected by the lateral encroachment of CoSi₂ layer into the channel direction when the gate spacer length was larger than 400 Å     

A novel elevated MOSFET source/drain structure

A vertically layered elevated drain structure is proposed which is suitable, in terms of reliability and performance for MOSFET scaling down to the 0.25-μm level without a reduction of the supply voltage below 3.3 V. In this structure, a low-doped polysilicon or crystalline silicon spacer (layer) is used to solve the hot-carrier problem. In contrast to existing device structures, which try to minimize the impact ionization rate, this structure rests on the idea that high-impact ionization and even high hot-carrier injection (HCl) rates can be tolerated as long as they are not detrimental to the device characteristics     

Improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region

An improved double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region was proposed. The recessed source/drain drift region is to reduce channel thickness between gate and drain as well as eliminate gate depletion layer extension to source/drain. The recessed source/drain drift region of the proposed structure can be realized with the formation of double-recessed gate region. The simulated results showed that the breakdown voltage of the proposed structure is 145 V compared to 109 V of that of the published 4H-SiC MESFETs with double-recessed gate structure and yet maintain almost same saturation drain current characteristics. The output power density of the proposed structure is about 33% larger than that of the published double-recessed gate structure. The cut-off frequency (f_T) and the maximum oscillation frequency (f_max) of the proposed structure are 21.8 GHz and 81.5 GHz compared to 19.0 GHz and 76.4 GHz of that of the published double-recessed gate structure, respectively.     

Impact of lateral source/drain abruptness on device performance

This paper presents a detailed study of the impact of lateral doping abruptness in the source/drain extension region and the gate-extension overlap length on device performance. Proper choice of the metric used to compare the different device designs is essential. Series resistance and threshold voltage roll-offs are shown to be incomplete measures of device performance that could lead to inconsistent lateral abruptness requirements. While series resistance is seen to improve with increasing junction abruptness, threshold voltage roll-off could be degraded by both lateral junctions that are too gradual and too abrupt - in contrast to the conventional scaling assumptions. The I/sub on/ (supernominal)-I/sub off/ (subnominal) plot, which takes into account statistical variations of gate length, is proposed as a good metric for comparing different device technology designs. Gate-extension overlap length is shown to interact with lateral doping abruptness and to have a significant impact on device performance.     

Self-aligned silicided (PtSi and CoSi2) ultra-shallow p+/n junctions

Ultra-shallow p+/n junctions (<100 nm) demonstrating excellent I-V characteristics have been fabricated with self-aligned PtSi. Junctions were formed by rapid thermal annealing (RTA) 〈100〉 Si preamorphized with Sn+ and implanted with BF2+. Subsequently, low-temperature RTA in N2of sputter-deposited Pt produced a 55-nm-thick PtSi layer possessing a remarkably smooth surface and interface, and demonstrating excellent resistance to the aqua regia etch solution. The silicided junctions displayed a sheet resistance of 14 Ω/sq with less than -2-nA . cm^-2reverse-bias leakage at -5 V. In a comparative scheme, similar junction characteristics were obtained using a self-aligned 39-nm-thick CoSi2overlayer.     

Interconnect design strategy: structures, repeaters and materialswith strategic system performance analysis (S2PAL) model

In this paper, we propose a novel methodology for scheming an interconnect strategy, such as what interconnect structure should be taken, how repeaters should be inserted, and when new metal or dielectric materials should be adopted. In the methodology, the strategic system performance analysis model is newly developed as a calculation model that predicts LSI operation frequency and chip size with electrical parameters of transistors and interconnects as well as circuit configuration. The analysis with the model indicates that interconnect delay overcomes circuit block cycle time at a specific length; D_c-cross. Here tentatively, interconnects shorter than D_c-cross are called local interconnects, and interconnects longer than that as global ones. The cross-sectional structures for local and global tiers are optimized separately. We also calculate global interconnect pitch and the chip size enlarged by the global interconnect pitch and the inserted repeaters, and then estimate the effectiveness of introducing new materials for interconnects and dielectrics     

High performance of pentacene organic thin film transistors by doping of iodine on source/drain regions

Contact doping was conducted by iodine in a top contact configuration in a pentacene organic thin film transistor (OTFT), to investigate its effects on contact resistance and the resulting electrical performance. Iodine doping in the pentacene film caused the change of pentacene structure, thus leading to an increase in electrical anisotropy, i.e. ratio of lateral to vertical resistivity. The two resistive components of doped pentacene film underneath the Au contacts were major contributors to the contact resistance, and a model to explain the dependence of contact resistance on iodine doping was presented. Finally, OTFTs fabricated on iodine doped source/drain contacts exhibited high mobility of 1.078 cm²/V s, two times that of OTFTs with undoped contacts, due to the low contact resistance.     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

An analytical method for determining intrinsic drain/source resistance of lightly doped drain (LDD) devices

MOS devices with double diffusion junctions containing Lightly Doped Drain/Source (LDD) regions have been built and analyzed. Comparison of current characteristics of the 2 μ m LDD devices with conventional devices of same channel length indicates that the LDD devices, while displaying relatively good drain current gain, deviate from the MOS transistors in the linear region due to the intrinsic n^? drain/source resistance and thus have lower substrate current due to the reduced hot electron effects. An analytical method is developed where this intrinsic resistance can be extracted from curve fitting of I–V data. Through curve fitting analysis the intrinsic resistance parameter is found to be an inverse function of transistor width as well as being dependent on temperature in the usual $\text{T}{}^{\mathrm{<mtext>3</mtext><mtext>2</mtext>}}$ manner.     

High mobility Ge-on-insulator p-channel MOSFETs using Pt germanide Schottky source/drain

We demonstrate, for the first time, successful operation of Schottky-barrier source/drain (S/D) germanium-on-insulator (GOI) MOSFETs, where a buried oxide and a silicon substrate are used as a gate dielectric and a bottom gate electrode, respectively. Excellent performance of p-type MOSFETs using Pt germanide S/D is presented in the accumulation mode. The hole mobility enhancement of 50%/spl sim/40% against the universal hole mobility of Si MOSFETs is obtained for the accumulated GOI channel with the SiO/sub 2/-Ge interface.     

A new asymmetrical halo source GOLD drain (HS-GOLD) deepsub-half-micrometer n-MOSFET design for reliability and performance

An asymmetrical n-MOSFET device structure was developed that is suitable, in terms of reliability and performance, for scaling down to the sub-quarter-micrometer level without reduction of the supply voltage below 3.5 V. In this structure, large-tilt implantation is used to form the gate-overlapped LDD (GOLD) region at the drain electrode only. A halo (punchthrough stopper) is used at the source, but not at the drain. Superior hot carrier reliability and high punchthrough resistance are obtained using this device structure. A reliability-limited supply voltage of 4.2 V is obtained for an asymmetrical n-MOSFET with effective channel lengths as short as 0.25 μm. By extrapolation from the measured threshold roll-off characteristics, the authors expect that this structure can be designed with substantially shorter channel length while maintaining the 3.5-V supply voltage     

Simple source/drain contact structure for solution-processed n-channel fullerene thin-film transistors

This paper describes a simple approach for reducing the contact resistances at the source/drain (S/D) contacts in solution-processed n-channel organic thin-film transistors (OTFTs). Blending poly(ethylene glycol) (PEG) into the fullerene semiconducting layer significantly improved the device performance. The PEG molecules in the blends underwent chemical reactions with the Al atoms of the electrodes, thereby forming a better organic-metal interface. Further, the rougher surface obtained after the addition of PEG could also increase the effective contact area, thereby reducing the resistance. As a result, the electrical properties of the devices were significantly improved. Unlike conventional bilayer structures, this approach allows the ready preparation of OTFTs with a low electron injection barrier at the S/D contacts.     

A new cell structure with a spread source/drain (SSD) MOSFET and acylindrical capacitor for 64-Mb DRAM's

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs     

Solution-processed organic field-effect transistors composed of poly(4-styrene sulfonate) wrapped multiwalled carbon nanotube source/drain electrodes

Multiwalled carbon nanotubes (MWNTs) were solubilized in water by wrapping them noncovalently with poly(4-styrene sulfonate) (PSS). The PSS-wrapped MWNTs exhibited a high conductivity (2.0 × 10² S/cm) when compared to other solution-processed electrodes. Ultraviolet photoelectron spectroscopy results show the PSS-wrapped nanotubes have a work function of 4.83 eV, which is 0.36 eV higher than that of untreated MWNTs. We fabricated triisopropylsilylethynyl pentacene field-effect transistors (FETs) using the PSS-wrapped MWNTs as source/drain electrodes and found that the field-effect mobility of the thus obtained devices was 0.043 cm² V^?1 s^?2. This mobility is four times higher than that of similar FETs containing gold electrodes (0.011 cm² V^?1 s^?2).     

Influence of asymmetric/symmetric source/drain region on asymmetryand mismatch of CMOSFET's and circuit performance

Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5-μm surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated with four ion-implantation methods and designed with a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry in MOSFETs with a one-sided 7°-implantation method. The symmetric 7°×4-implantation method gives good A&M characteristics of n- and p-MOSFET's with the both layouts. According to the circuit performance of ring oscillators, the ion-implantation method is correlated to supply-current/oscillation-frequency/delay-power product and substrate current. The symmetric 7°×4-implantation method is the most preferable in terms of A&M and punchthrough immunity of CMOSFET as well as circuit performance     

基于沟道及电极修饰的酞菁铜场效应晶体管的性能提高研究

利用对四联苯p -4P 以及五氧化二钒V2O5同时修饰导电沟道及源/漏电极,大幅 提高了基于酞菁铜CuPc场效应晶体管的性能。本文通过在绝缘层SiO2和有源层CuPc 之间插入p-4p缓冲薄层,同时在源/漏电极Al与有机半导体之间引入电极修饰层V2O5, 使得CuPc场效应晶体管的饱和迁移率和电流开/关比分别提高到5×10-2cm2 / V s和 104。p -4P能够诱导p型CuPc形成高度取向的连续薄膜,使得载流子能够在有源层中 更好地传输;而V2O5能够调节载流子的注入势垒,并可有效地降低沟道接触电阻(Rc)。 此方法能够在降低器件制备成本的前提下,大幅提高器件的性能。     

A polysilicon source and drain MOS transistor (PSD MOST)

An MOS transistor is described in which the source and drain areas are obtained by diffusion from doped polycrystalline silicon. Polysilicon tracks form the interconnect with the diffusion areas without the need for contact windows. As a result transistor and junction sizes are reduced by a factor 2 or 3 over a normal structure. Polycrystalline silicon tracks in this new technique are of greater advantage as interconnect layers than in the silicon gate tecgnique.