A Novel Balanced MMIC Frequency Multiplier Configuration

A characterisation method, suitable for the study of balanced MMIC frequency multiplier circuits is presented. Using this approach, a number of frequency doubler and tripler configurations are considered. The influence of the non-ideal amplitude/phase balance characteristics of some planar hybrids on the harmonic rejection properties of these circuits is discussed. Optimum circuit configurations for doubler and tripler applications are proposed. Design details for a novel generalised configuration, which can be utilised for the balancing of single-ended multiplier circuits of any order, are outlined. The harmonic generation characteristics inherent in this approach are discussed.     

The W-Band High Order Avalanche Diode Frequency Multiplier

The high degree nonlinearity properties of avalanche diode render itself suitable for high order frequency multiplication in a single stage. This paper first analyzes the mechanism of multiplication mode, and introduces the principle of high order frequency multiplier. In experiment, the multiplier has achieved maximum 7 dBm output power and 19 dB conversion loss at the output frequency of 94.5 GHz with 15th multiplication order.     

A Novel W-band Microstrip Integrated Avalanche Diode High Order Frequency Multiplier

A W band microstrip integrated high order frequency multiplier based on avalanche diode is proposed. The property of avalanche high order multiplication mode is analyzed based on physical operation mechanism of avalanche diode. According to the harmonics impedance model of avalanche diode, the microstrip integrated multiplier is designed, fabricated and measured. Output power of 5.78 mW has been obtained at output frequency of 94.5 GHz with 15th multiplication order and the phase noise is -90 dBc/Hz and -95 dBc/Hz at 10 KHz and 100 KHz offset. Good results at 13th and 17th multiplication order are also obtained.     

Low Noise mm-Wave Amplifier Design Methodology

A design methodology for mm-wave LNAs is presented. The optimum bias point selection is outlined. The stabilisation strategy is described, and the impact of packaging requirements on the amplifier design is discussed. A bond wire compensation technique is detailed. The tradeoff between input match and noise figure is presented, and a design with a suitable tradeoff is¹ developed. A very simple inter-stage match requirement is a novel outcome of this design approach. An effective means of achieving a broadband response is also outlined. A four stage 30 – 50 GHz LNA design was fabricated and characterised in a customised package. A maximum MMIC gain of 28 dB at 32 GHz was achieved, and the gain exceeded 20 dB over the frequency range 26 – 44 GHz. A noise figure of 4.5 dB and a P1dB of +11 dBm were also obtained. It is the authors' opinion that the methodology presented in this paper will be of significant interest to other mm-wave LNA designers.     

Optical Generation of mm-Wave Signal Through Optoelectronic Phase-Locked Loop

In this paper, we propose a scheme for the generation of low phase noise tunable mm-wave signal by beating two lightwaves in a photodiode. These two lightwaves are made phase coherent by an optoelectronic phase locked loop.Calculated mm-wave power at a frequency of 60 GHz is found to be -4 dBm.     

Theoretical Study of the Frequency Multiplier Based on Irregular Quarter-Wavelength Microstrip Resonator with Thin Magnetic Film

Russian Physics Journal - The characteristics of a frequency doubler on a resonant microstrip structure with a thin magnetic film were studied theoretically. The electrodynamic calculation of the...     

一种小型化铷原子钟锁相倍频窄带VCO设计

设计了一款用于小型化铷原子钟锁相倍频器的窄带VCO(压控振荡器)电路.振荡电路采用了稳定性好的克拉泼电路方案.应用仿真软件对该电路进行仿真分析和优化设计.最终设计出的VCO电路主要性能指标为:输出频率范围为440 MHz~470 MHz,频率调谐灵敏度为18 MHz/V,二次谐波抑制度为-15 d Bc,由其构成的锁相倍频器实现了低相噪设计要求,使小型化铷原子钟具备了实现高的频率稳定度潜力.     

Accurate Small-Signal Model Extraction for pHEMT on GaAs

An accurate small-signal modeling approach applied to GaAs-based pHEMT devices is presented. The procedure for extracting equivalent-circuit model parameters is illustrated in detail. A genetic algorithm (GA) program is developed to optimize the model parameters in order to improve the modeling accuracy. The validity of modeling approach is verified by comparing the simulated and measured result of two pHEMTs and a fabricated ka-band power amplifier. The conclusion can be drawn that the proposed modeling method is rather accurate and efficient.     

Photonic mm-Wave Generation Using a Double Passband Fiber Bragg Grating Filter

We report a simplified version of a mm-wave generator employing the sideband filtering technique which uses a single optical sideband filter. Instead of using a Mach-Zehnder-like fiber network to select a pair of sidebands, we employ a single Fabry-Perot fiber Bragg grating with a pair of passbands separated by the mm-wave frequency. Using a single filter eliminated the need for polarization control and pathlength matching that was required by the former interferometer-like arrangement. We describe a 30 GHz generator design and present its mm-wave signal spectrum showing an instrument-limited linewidth of ~20 Hz. The generation of such an extremely narrow signal spectrum from a laser with a 1 MHz linewidth demonstrates the remarkable laser frequency noise cancellation property of the sideband filtering technique.     

Full-Duplex Radio-over-Fiber System Based on a Novel Octupling mm-Wave Generation Scheme

Abstract

A novel mm-wave generation scheme based on two phase modulators and two unbalanced Mach-Zehnder interferometers is proposed. Compared with the conventional Mach-Zehnder modulator-based scheme, the phase-modulator-based scheme can work steadily without an electrical control circuit for the DC bias, and it has smaller insertion loss. A full-duplex radio-over-fiber system was investigated by simulation, and its performance is not affected by chromatic dispersion for both downstream and upstream transmission. A 40-GHz mm-wave is generated from a 5-GHz driving signal. The system performance is analyzed by using eye diagrams and bit error rate. Results demonstrate that the performance is still very good, even after a 50-km transmission.     

基于实际空间截止频率的稀疏孔径双圆周阵列的优化

提出了一种新的稀疏孔径光瞳结构-两个圆周阵内外嵌套而成的双圆周结构,并研究了该结构的调制传递函数.该结构以实际空间截止频率作为约束条件,保证调制传递函数在最小截止频率以内无零频,以阵列的u-v覆盖点间距最大化及最小冗余度来设计目标函数,并采用这种优化方法对3-3、5-3以及6-3双圆周阵列进行了优化排列.将优化结果与相同子孔径数目的均匀圆周阵以及Golay结构进行仿真实验和比较.结果表明,优化后的双圆周阵列,具有最大的实际空间截止频率和实际等效口径.     

基于实际空间截止频率的稀疏孔径双圆周阵列的优化

提出了一种新的稀疏孔径光瞳结构—两个圆周阵内外嵌套而成的双圆周结构,并研究了该结构的调制传递函数.该结构以实际空间截止频率作为约束条件,保证调制传递函数在最小截止频率以内无零频,以阵列的u－v覆盖点间距最大化及最小冗余度来设计目标函数,并采用这种优化方法对3-3、5-3以及6-3双圆周阵列进行了优化排列.将优化结果与相同子孔径数目的均匀圆周阵以及Golay结构进行仿真实验和比较.结果表明,优化后的双圆周阵列,具有最大的实际空间截止频率和实际等效口径.     

Heterogeneous integration of GaAs pHEMT and Si CMOS on the same chip

In this work,we demonstrate the technology of wafer-scale transistor-level heterogeneous integration of Ga As pseudomorphic high electron mobility transistors(p HEMTs) and Si complementary metal–oxide semiconductor(CMOS) on the same Silicon substrate.Ga As p HEMTs are vertical stacked at the top of the Si CMOS wafer using a wafer bonding technique,and the best alignment accuracy of 5 μm is obtained.As a circuit example,a wide band Ga As digital controlled switch is fabricated,which features the technologies of a digital control circuit in Si CMOS and a switch circuit in Ga As p HEMT,15% smaller than the area of normal Ga As and Si CMOS circuits.     

电荷载流子倍增寄存器中的倍增噪声

信号电荷在电荷载流子倍增寄存器中的强场下,吸收电场能量激发碰撞电离过程。电子碰撞电离过程激发的电子-空穴对具有独立性和随机性,其激发过程产生的倍增噪声主要是散粒噪声。借助于马尔可夫链定理,得到了CCM单元的倍增因子的计算方法,建立了电子碰撞电离的数学模型。在此基础上,推导了CCM单元倍增噪声的功率谱密度,表明其与倍增因子相关。     

Effective Designs of Reversible Vedic Multiplier

Power dissipation problem is one of the most challenging problems in designing conventional electronic circuits. One of the best approaches to overcome this problem is to design reversible circuits. Nowadays, reversible logic is considered as a new field of study that has various applications such as optical information processing, design of low power CMOS circuits, quantum computing, DNA computations, bioinformatics and nanotechnology. Due to the vulnerability of the digital circuits to different environmental factors, the design of circuits with error-detection capability is considered a necessity. Parity preserving technique is known as one of the most famous methods for providing error-detection ability. Multiplication operation is considered as one of the most important operations in computing systems, which can play a significant role in increasing the efficiency of such systems. In this paper, two efficient 4-bit reversible multipliers are proposed using the Vedic technique. The Vedic technique is able to increase the speed of multiplication operation by producing partial products and their sums simultaneously in a parallel manner. The first architecture lacks the parity preserving potential, while the second architecture has the ability parity preserving. Since a 4-bit Vedic multiplier includes 2-bit Vedic multipliers and 4-bit ripple carry adders (RCA), so in the first design, TG, PG and FG gates have been used to design an efficient 2-bit reversible Vedic multiplier, as well as PG gate and HNG block have been applied as a half-adder (HA) and full-adder (FA) in the 4-bit RCAs. Also, in the second design, 2-bit parity preserving reversible Vedic multiplier has been designed using FRG, DFG, ZCG and PPTG gates as well as ZCG and ZPLG blocks have been utilized as HA and FA in the 4-bit RCAs. Proposed designs are compared in terms of evaluation criteria of circuits such as gate count (GC), number of constant inputs (CI), number of garbage outputs (GO), quantum cost (QC), and hardware complexity. The results of the comparisons indicate that the proposed designs are more efficient compared to available counterparts.

     

Designing of Parity Preserving Reversible Vedic Multiplier

International Journal of Theoretical Physics - Reversible logic is used in designing low-power CMOS circuits, optical information processing, and quantum computing. Moreover, using parity...     

微球板电子倍增器基体制备技术研究

新型微球板电子倍增器和微通道板相比具有高增益、无离子反馈、制备简单、造价低廉等优点。介绍了微球板电子倍增器的工作原理、特点和广阔的应用前景。由于微球板基体的形成技术是微球板制备的关键技术，论文从理论上研究了微球板基体烧结过程中的烧结速率。并采用自行设计组分的高铅玻璃，用立式炉成珠设备进行了玻璃微珠的制备。探索了微球板制备过程中玻璃微珠的分级技术、微球板电子倍增器基体成型工艺和技术。制备出基本满足要求的微球板电子倍增器基体。给出了制造的样品和文献上样品结构的SEM对比照片，最后对实验过程中的一些现象进行了分析，并给出了实验的结论。     

large Last Multiplier of Generalized Hamilton System

We study an application of the Jacobi last multiplier to a generalized Hamilton system. A partial differential equation on the last multiplier of the system is established. The last multiplier can be found by the equation. If the quantity of integrals of the system is sufficient, the solution of the system can be found by the last multiplier.     

T-Count Optimized Wallace Tree Integer Multiplier for Quantum Computing

International Journal of Theoretical Physics - Quantum circuits for performing an arithmetic operation are necessary for the implementation of quantum computing peripherals. An effective quantum...