High-power SiC MESFET using a dual p-buffer layer for an S-band power amplifier

A silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is fabricated by using a standard SiC MESFET structure with the application of a dual p-buffer layer and a multi-recessed gate to the process for an S-band power amplifier. The lower doped upper-buffer layer serves to maintain the channel current, while the higher doped lower-buffer layer is used to provide excellent electron confinement in the channel layer. A 20-mm gate periphery SiC MESFET biased at a drain voltage of 85 V demonstrates a pulsed wave saturated output power of 94 W, a linear gain of 11.7 dB, and a maximum power added efficiency of 24.3% at 3.4 GHz. These results are improved compared with those of the conventional single p-buffer MESFET fabricated in this work using the same process. A radio-frequency power output greater than 4.7 W/mm is achieved, showing the potential as a high-voltage operation device for high-power solid-state amplifier applications.     

High-power SiC MESFET using dual p-buffer layer for S-band power amplifier

Silicon carbide (SiC) based metal semiconductor field effect transistor (MESFET) is fabricated by using a standard SiC MESFET structure with the application of a dual p-buffer layer and a multi-recessed gate to the process for S-band power amplifier. The lower doped upper-buffer layer serves to maintain the channel current, while the higher doped lower-buffer layer is used to provide excellent electron confinement in the channel layer. A 20-mm gate periphery SiC MESFET biased at a drain voltage of 85 V demonstrates a pulsed wave saturated output power of 94 W, a linear gain of 11.7 dB, and a maximum power added efficiency of 24.3% at 3.4 GHz. These results are improved compared with those of the conventional single p-buffer MESFET fabricated in this work using the same process. A radio-frequency power output greater than 4.7 W/mm is achieved, showing the potential as a high-voltage operation device for high-power solid-state amplifier applications.     

Physical simulations and experimental results of 4H—SiC MESFETs on high purity semi-insulating substrates

In this paper we report on DC and RF simulations and experimental results of 4H--SiC metal semiconductor field effect transistors (MESFETs) on high purity semi-insulating substrates. DC and small-signal measurements are compared with simulations. We design our device process to fabricate n-channel 4H--SiC MESFETs with 100~μm gate periphery. At 30~V drain voltage, the maximum current density is 440~mA/mm and the maximum transconductance is 33~mS/mm. For the continuous wave (CW) at a frequency of 2~GHz, the maximum output power density is measured to be 6.6~W/mm, with a gain of 12~dB and power-added efficiency of 33.7％. The cut-off frequency (f_T) and the maximum frequency (f_max) are 9~GHz and 24.9~GHz respectively. The simulation results of f_T and f_max are 11.4~GHz and 38.6~GHz respectively.     

SIMPLE TECHNIQUES FOR DETERMINING THE SMALL-SIGNAL EQUIVALENT CIRCUIT OF MESFET’s

Simple techniques for determining the broadband small signal equivalent circuit (SSEC) of MESFETs are presented in this paper. The intrinsic elements are calculated using two-dimensional method from the Y parameters, which are obtained from the Fourier analysis of the device transient response to voltage-step perturbations at the drain and gate electrodes. Whereas, the parasitic external elements are determined by simple approximations used in transmission line modeling. In addition, a new technique is also proposed to determine the source and drain series resistances. A comparison of the SSEC of three different MESFETs technologies shows that the MESFETs on GaN and 4H-SiC are suitable for high power applications. The method used to determine the intrinsic elements is validated with simulated data obtained by Monte Carlo method.     

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metalben semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.     

Effects of gate-buffer combined with a p-type spacer structure on silicon carbide metal-semiconductor field-effect transistors

An improved structure of silicon carbide metal-semiconductor field-effect transistors (MESFET) is proposed for high power microwave applications. Numerical models for the physical and electrical mechanisms of the device are presented, and the static and dynamic electrical performances are analysed. By comparison with the conventional structure, the proposed structure exhibits a superior frequency response while possessing better DC characteristics. A p-type spacer layer, inserted between the oxide and the channel, is shown to suppress the surface trap effect and improve the distribution of the electric field at the gate edge. Meanwhile, a lightly doped n-type buffer layer under the gate reduces depletion in the channel, resulting in an increase in the output current and a reduction in the gate-capacitance. The structural parameter dependences of the device performance are discussed, and an optimized design is obtained. The results show that the maximum saturation current density of 325 mA/mm is yielded, compared with 182 mA/mm for conventional MESFETs under the condition that the breakdown voltage of the proposed MESFET is larger than that of the conventional MESFET, leading to an increase of 79% in the output power density. In addition, improvements of 27% cut-off frequency and 28% maximum oscillation frequency are achieved compared with a conventional MESFET, respectively.     

Fabrication of ultra-short gate MESFETs and BlochFETS by electron beam lithography

We have used electron beam lithography in single level PMMA to investigate both ultra-submicron gate MESFETs and a novel quantum device called a BlochFET. From d.c. transconductance (g_m) measurements of MESFETs with gate lengths from 35 to 65 nm, our data indicate a rise in g_m below 50 nm which we attribute to the onset of velocity overshoot. The BlochFETs and HEMTs whose gates are replaced by a lateral surface superlattice grid structure. These grids are composed of 40 nm lines on 170 nm pitch. We have observed negative differential conductance which may be due to Bloch oscillation effects at low temperatures and believe this to be the first such observation yet reported.     

Optical modulation of the effective channel thickness in GaAs field effect transistors with a Schottky gate (MESFETs)

Using a model relating the change in drain current with modulation of the effective channel thickness upon IR illumination of GaAs field effect transistors with a Schottky gate (MESFETs), it is shown that it is possible to determine the change in channel thickness and the concentration profile for deep centers in an FET channel. Profiles are given for the distribution of deep centers in the channels of GaAs MESFETs with different noise temperatures. __________ Translated from Zhurnal Prikladnoi Spektroskopii, Vol. 73, No. 3, pp. 349–353, May–June, 2006.     

In–Ga–Zn–O MESFET with transparent amorphous Ru–Si–O Schottky barrier

Rectifying transparent amorphous Ru–Si–O Schottky contacts to In–Ga–Zn–O have been fabricated by means of reactive sputtering without any annealing processes nor semiconductor surface treatments. The ideality factor, effective Schottky barrier height and rectification ratio are equal to 1.6, 0.9 eV and 10⁵ A/A, respectively. Ru–Si–O/In–Ga–Zn–O Schottky barriers were employed as gate electrodes for In–Ga–Zn–O metal–semiconductor field‐effect transistors (MESFETs). MESFET devices exhibiting on‐to‐off current ratio at the level of 10³ A/A in a voltage range of 2 V, with subthreshold swing equal to 420 mV/dec were demonstrated. A channel mobility of 7.36 cm²/V s was achieved. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Electron beam lithographic fabrication of ultra-submicron gate GaAs MESFETs

A single-level-resist process was used to fabricate GaAs MESFETs with gate lengths as short as 28 nm on MBE grown epi-layers. D.C. measurements yielded transconductances up to 85 mS/mm with no dependence on gate length.     

Theoretical investigation of incomplete ionization of dopants in uniform and ion-implanted 4H-SiC MESFETs

The effects of incomplete ionization of nitrogen in 4H-SiC have been investigated. Poisson's equation is numerically analysed by considering the effects of Poole--Frenkel, and the effects of the potential on $N^+_\dd$ (the concentration of ionized donors) and $n$ (the concentration of electrons). The pinch-off voltages of the uniform and the ion-implanted channels of 4H-SiC metal-semiconductor field-effect transistors (MESFETs) and the capacitance of the gate are given at different temperatures. Both the Poole--Frenkel effect and the potential have influence on the pinch-off voltage $V_{\rm p}$ of 4H-SiC MESFETs. Although the $C$-$V$ characteristics of the ion-implanted and the uniform channel of 4H-SiC MESFETs have a clear distinction, the effects of incomplete ionization on the $C$-$V$ characteristics are not significant.     

AlGaN/GaN high-electron-mobility transistors with transparent gates by Al-doped ZnO

AlGaN/GaN high-electron-mobility transistors （HEMTs） with Al-doped ZnO （AZO） transparent gate electrodes are fabricated, and Ni/Au/Ni-gated HEMTs are produced in comparison. The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics, and the gate electrodes achieve excellent transparencies. Compared with Ni/Au/Ni-gated HEMTs, AZO-gated HEMTs show a low saturation current, high threshold voltage, high Schottky barrier height, and low gate reverse leakage current. Due to the higher gate resistivity, AZO-gated HEMTs exhibit a current-gain cutoff frequency （fT） of 10 GHz and a power gain cutoff frequency （fmax） of 5 GHz, and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs. Moreover, the C-V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C-V dual sweep.     

High temperature characteristics of ZnO-based MOS-FETs with a photochemical vapor deposition SiO2 gate dielectric

The authors report the fabrication of ZnO-based metal-oxide-semiconductor field effect transistors (MOSFETs) with a high quality SiO₂ gate dielectric by photochemical vapor deposition (photo-CVD) on a sapphire substrate. Compared with ZnO-based metal-semiconductor FETs (MESFETs), it was found that the gate leakage current was decreased to more than two orders of magnitude by inserting the photo-CVD SiO₂ gate dielectric between ZnO and gate metal. Besides, it was also found that the fabricated ZnO MOSFETs can achieve normal operation of FET, even operated at 150 °C. This could be attributed to the high quality of photo-CVD SiO₂ layer. With a 2 μm gate length, the saturated I_ds and maximum transconductance (G_m) were 61.1 mA/mm and 10.2 mS/mm for ZnO-based MOSFETs measured at room temperature, while 45.7 mA/mm and 7.67 mS/mm for that measured at 150 °C, respectively.     

Improved performance of 4H-SiC metal-semiconductor field-effect transistors with step p-buffer layer

An improved 4H-SiC metal-semiconductor field-effect transistors (MESFETs) with step p-buffer layer is proposed, and the static and dynamic electrical performances are analysed in this paper. A step p-buffer layer has been applied not only to increase the channel current, but also to improve the transconductance. This is due to the fact that the variation in p-buffer layer depth leads to the decrease in parasitic series resistance resulting from the change in the active channel thickness and modulation in the electric field distribution inside the channel. Detailed numerical simulations demonstrate that the saturation drain current and the maximum theoretical output power density of the proposed structure are about 30% and 37% larger than those of the conventional structure. The cut-off frequency and the maximum oscillation frequency of the proposed MESFETs are 14.5 and 62 GHz, respectively, which are higher than that of the conventional structure. Therefore, the 4H-SiC MESFETs with step p-buffer layer have superior direct-current and radio-frequency performances compared to the similar devices based on the conventional structure.     

二次耦合直流输出的金属氧化物TFT行驱动电路

为了弥补现有氧化物TFT的行驱动电路输出模块在功率消耗、响应速度、输出摆幅等方面的不足,提出了基于二次耦合的直流输出模块,并由此研究设计新的行驱动电路拓扑。仿真结果表明,该输出模块具有驱动能力强、响应速度快等优点。最后,基于刻蚀阻挡层(ESL)结构的氧化物TFT工艺,在玻璃衬底上成功制备了该行驱动电路,实测单级功耗为325μW。     

深亚微米SOI射频 LDMOS功率特性研究

提出了一种SOI LDMOS大信号等效电路模型,并给出了功率增益和输入阻抗表达式. 基于制备的深亚微米SOI射频LDMOS,测试了功率增益和功率附加效率. 深入研究了SOI LDMOS功率特性与栅长,单指宽度,工作电压和频率之间关系. 栅长由0.5 μm减到0.35 μm时,小信号功率增益增加44％,功率附加效率峰值增加9％. 单指宽度由20 μm增加到40 μm,600 μm /0.5 μm器件小信号功率增益降低23％,功率附加效率峰值降低9.3％. 漏端电压由3 V增加到5 V,600 μm /0.3 关键词： SOI射频 LDMOS 深亚微米 功率增益 功率附加效率     

Step-by-step implementation of an amplifier circuit with a graphene field-effect transistor on a printed-circuit board

Power amplifier circuits are implemented with graphene field-effect transistors (FETs), capacitors and inductors, and their gain is improved step-by-step by adjusting the passive components. The transistors are fabricated on a 150-mm wafer using conventional complementary-metal-oxide semiconductor processing along with graphene transferring processes. The completed circuit is implemented on a printed circuit board, which allows for adjustment of the external capacitance and inductance to study the performance of graphene RF FETs. A maximum signal gain of 1.3 dB is achieved at 380 MHz. The device parameters of the transistors are then extracted and the gain is analyzed, and the results show that lowering the source–drain conductance and gate resistance is the key in realizing high performance circuits.     

Electron traps and positive DLTS signals in VPE GaAs MESFETs

Capacitance DLTS measurements have been performed in VPE GaAs MESFETs prepared on Bridgman Cr-doped and LEC undoped semi-insulating substrates. A band of electron traps not intrinsically related to the VPE growth process and accumulating near the metal (gate) — semiconductor interface was detected in all the samples. Deeper regions into the channel were free from any detectable trap. Near pinch-off conditions, a positive capacitance signal was found to dominate the DLTS spectra only in the case of samples prepared on Cr-doped substrates. The hypothesis of this positive transient being related to changes in the occupation of surface states in the ungated surface access regions has been checked by comparing experimental and calculated dependencies of the signal amplitude on reverse gate voltage. Unexplained discrepancies, together with the absence of positive signal in MESFETs prepared on LEC undoped substrates, suggest the possibility of hole emission from hole traps within the bulk of the device.     

Application of superlattice gate and modulation-doped buffer for GaAs power MESFET grown by MBE

A new power GaAs MESFET (SGMBT), using the undoped superlattice gate and modulation-doped (MD) buffer, has been fabricated successfully by MBE. A much higher gate-drain breakdown voltage (30 V) and lower gate reverse leakage current have been obtained due to the existence of the undoped AlGaAs/GaAs superlattice gate insulator. The use of MD buffer structure introduces a high output resistance and low trap concentration at AlGaAs/GaAs interface. The degradation region at channel-buffer interface is estimated to be smaller than 40 Å. Thus the sharpness and smoothness between active channel and buffer is truly improved by the insertion of MD structure. The maximum output saturation current and output power of SGMBT are 300 mA/mm and 0.67 W/mm, respectively. By optimizing the device geometry and gate dimension, the output performance of SGMBT can be improved further.     

新型低功耗金属氧化物TFT集成行驱动电路

金属氧化物薄膜晶体管(TFT)属于耗尽型器件,其集成的TFT的行驱动电路一般采用双负电源方案,存在与外围驱动芯片的匹配困难和功耗较大的不足。本文设计了一种新型耦合电路结构,可以产生比负电源更低的电压从而完全关闭输出模块的下拉晶体管,防止氧化物TFT耗尽模式引起的电流泄露问题,并由此设计了新型氧化物TFT行驱动电路拓扑。由于只采用一个负电源,其电源电压范围比采用双负电源方案的小,从而节省了功耗且有利于与外围驱动芯片的匹配连接。实验结果表明,基于刻蚀阻挡层(ESL)结构的氧化物TFT工艺,在玻璃衬底上成功制备了该行驱动电路,在电阻负载R L=3 kΩ和容性负载C L=30 pF下,所设计的行驱动电路在33.3 kHz时钟频率下实现脉宽10μs的全摆幅输出,每级功耗仅为160μW。基于新型耦合电路结构的行驱动电路能够满足60 Hz的刷新频率的1980×1080分辨率的显示需求。