Reliability testing of InP HEMT's using electrical stress methods

In this paper, we discuss the results of three different electrical stress tests on InP-based HEMT's and their implications toward reliability. These are hot electron (HE) stress, transmission line pulse (TLP) measurements, and RF overdrive stress. Some processing parameters have been varied to investigate their influence on reliability issues. HE stress is performed on a set of Si₃N ₄ passivated devices with increasing recess width. Degradation is observed to be largely dependent on recess width, due to changes at the InAlAs-Si₃N₄ interface. With TLP measurements, an ESD-like reliability study is performed on devices with different types of Schottky barriers. Although epilayers with In_0.40Al_0.00 as Schottky material show improved breakdown and leakage characteristics over In_0.52Al_0.48 As, pulsed stress tests reveal an earlier breakdown. Finally, the degradation under large-signal RF overdrive stress is determined with a nonlinear network measurement system (NNMS). Both on- and off-state degradation are studied with this set-up. Results appeared to be strongly dependent on the phase difference between the stress voltage waves applied at the device ports     

Highly uniform N-InAlAs/InGaAs HEMT's on a 3-in InP substrate usingphotochemical selective dry recess etching

Large-area photochemical selective dry etching has been developed for use in InGaAs/InAlAs heterojunction fabrication involving CH₃ Br gas and a low-pressure mercury lamp. The etch rate of the InGaAs layer was 17 nm/min and the etch ratio of InGaAs to InAlAs was around 25 to 1. The dry recess was performed for N-InAlAs/InGaAs HEMT's on a 3-in wafer using photochemical etching. The standard deviation of the threshold voltage across the wafer was 18 mV at a threshold voltage of -0.95 V, and the transconductance of 456 mS/mm was obtained for a 1.1-μm-long gate within a standard deviation of 14.9 mS/mm     

An analytic model for HEMT's using new velocity-field dependence

An analytic model is developed for the output current-voltage characteristics and microwave-signal parameters of high electron mobility transistors (HEMT's). In this model, the GSW equation is used to approach the behavior of electron drift velocity versus electric field. The resulting I-V curves are in excellent agreement with experimental data. In order to predict the microwave performance of these devices, this model is then used to derive the small-signal parameters, transconductance, channel conductance, and gate capacitance.     

InP衬底上晶格匹配四元系InAlGaAs的气态源分子束外延生长

采用高分辨率X射线衍射摇摆曲线、光致发光以及霍尔测试对采用气态源分子束外延方法生长的四元系In-AlGaAs材料性质进行了表征。摇摆曲线结果表明,根据计算数据所生长的InAlGaAs样品与InP衬底基本匹配.光致发光和霍尔测试结果显示随着Al组分的增加,样品的光致发光强度、电子浓度和迁移率均有所下降.样品的三族元素组分由光致发光及X射线衍射实验获得,测试结果与设计值吻合,Al组分的实验设计值与测试结果的关系提供了一种实用的精确控制组分的方法.     

Modeling of current-voltage characteristics of thin film solar cells

An analytical model is developed to study the current-voltage characteristics of thin film solar cells by incorporating exponential photon absorption, carrier trapping and carrier drift in the absorber layer. An analytical expression for the external voltage dependent photocurrent is derived by solving the continuity equation for both electrons and holes assuming the electric field remains uniform in the absorber layer. The analytical results are verified with the numerical self-consistent solution of the steady-state continuity equations and the Poisson’s equation. The overall load current is calculated considering the actual solar spectrum. It is found that the solar cell efficiency critically depends on the transport properties of the carriers that drift towards the bottom contact. The recombination current dominates over the ideal diode current in CdTe based solar cells. The theoretical model is fitted with the published experimental data on various thin film solar cells and shows a very good agreement.     

Fabrication of strained Ge film using a thin SiGe virtual substrate

epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.     

采用薄SiGe虚拟衬底制备应变Ge材料

This paper describes a method using both reduced pressure chemical vapor deposition （RPCVD） and ultrahigh vacuum chemical vapor deposition （UHVCVD） to grow a thin compressively strained Ge film. As the first step, low temperature RPCVD was used to grow a fully relaxed SiGe virtual substrate layer at 500 ℃ with a thickness of 135 nm, surface roughness of 0.3 nm, and Ge content of 77%. Then, low temperature UHVCVD was used to grow a high quality strained pure Ge film on the SiGe virtual substrate at 300 ℃ with a thickness of 9 nm, surface roughness of 0.4 nm, and threading dislocation density of - 10^5 cm^-2. Finally, a very thin strained Si layer of 1.5-2 nm thickness was grown on the Ge layer at 550 ℃ for the purpose of passivation and protection. The whole epitaxial layer thickness is less than 150 nm. Due to the low growth temperature, the two-dimensional layer-by-layer growth mode dominates during the epitaxial process, which is a key factor for the growth of high quality strained Ge films.     

Refined model for the current-voltage characteristics of quantum-well infrared photodetectors

The temperature dependences of the dark current of quantum-well infrared photodetectors are investigated experimentally. It is established that the pre-exponential factor in the analytical expression for the photodetector current-voltage characteristics varies linearly with temperature. On the basis of the results obtained, it is suggested that the temperature dependence of the photodetector??s dark current is determined by the thermal excitation of charge carriers to a band characterized by a two-dimensional density of states. In the context of this suggestion, a refined model for the current-voltage characteristics is proposed. The model takes into account the thermal generation of charge carriers in a band with a two-dimensional density of states and the electric field dependence of the thermal activation energy for the quantum-well ground state and of the drift velocity of the carriers in the barrier conduction band.     

A theoretical model for the current-voltage characteristics of afloating-gate EEPROM cell

A model for current-voltage characteristics of an EEPROM cell has been developed and used in the simulation of an EEPROM test structure. It provides an explanation for the observed strong drain-induced barrier lowering effect and the role of trapped charge in the floating gate. In this model, the surface potential is related to the terminal voltages through an equivalent electrical circuit. Charge sheet and depletion approximation are used to describe the charge distribution in the semiconductor. Gradual approximation is assumed in deriving the drain current equation. A simplified drain current equation under a strong inversion condition is derived. An expression defining the extrapolated threshold voltage is obtained. It is useful in parameter extraction. A new method for extracting the drain coupling ratio and the channel coupling ratio is proposed. Finally, it is shown that extrapolated threshold voltage is a convenient quantity for classifying the threshold voltage of an EEPROM cell     

Analytical one-dimensional current-voltage model for FD SOI MOSFETs including the effect of substrate depletion

In this paper, we present an analytical one-dimensional current-voltage model for silicon-on-insulator (SOI) MOSFETs under full depletion (FD). Our model has been developed from the first principles, and it not only includes the effects of source-drain series resistances, self-heating, and parasitic BJT, which are essential to FD SOI device modeling, but also includes another important effect of substrate depletion, for the first time in the literature, which is of vital significance for FD SOI devices having small film thickness and low substrate doping. The results of the drain current obtained from our model show a much better match with the experimental data, with the maximum error being only 9.41%, which is reasonably lower than the maximum error of 15.04% produced by the model of Yu et al., and marginally better than the error of 11.5% of the model of Hu and Jang. It must be noted that, though the improvements achieved in terms of accuracy are not that significant, yet unlike other models, ours is based on a simplified one-dimensional analytical approach, which is absolutely free from iterations, and hence, there is a huge improvement in terms of computational efficiency, which establishes its practical significance.     

A universal electron mobility model of strained Si MOSFETs based on variational wave functions

A new model is proposed to describe the electron mobility enhancement in strained Si MOSFETs inversion layers using the variational wave functions in the triangular potential approximation. Phonon scattering and surface roughness scattering are included in this model and electron mobility enhancements due to the suppression of these two scatterings are accounted for, respectively. A process-dependent interface parameter is introduced to fit with various technologies. Results from the model show good agreement with experiments for different Ge mole fractions and for a wide range of vertical effective field and temperature. The model is very interesting for implementation in conventional device simulators.     

Lattice parameter determination of a strained area of an InAs layer on a GaAs substrate using CBED

All the six lattice parameters (a, b, c, alpha, beta and gamma) of a strained area of an InAs layer grown on a GaAs substrate were determined without any assumption of the crystal lattice symmetry from the higher-order Laue zone (HOLZ) lines appearing in one convergent-beam electron diffraction (CBED) pattern. The analysis was performed with three steps. Firstly, the parameters alpha and beta were determined from the deviations of the HOLZ lines from the mirror symmetry perpendicular to the [001] direction. Secondly, the parameter c was determined from the distance between the intersections of the HOLZ lines, which have the same h and k indices but different l indices. Finally, the parameters a, b and gamma were determined simultaneously from several distances between the intersections of the HOLZ lines. The lattice parameters determined for the strained area were a = 0.611(2) nm, b = 0.615(1) nm, c = 0.6119(7) nm, alpha = 89.5(1) degrees, beta = 89.0(2) degrees and gamma = 89.1(2) degrees. This result implies that the cubic lattice of InAs is elongated approximately in the [111] direction and the exact lattice symmetry is triclinic. The same analysis procedure was applied to another two specimen areas. It was found that the areas have orthorhombic distortions with lattice parameters a = 0.607(2) nm, b = 0.604(1) nm and c = 0.6085(7) nm for one area, and with a = 0.607(2) nm, b = 0.605(1) nm and c = 0.6065(7) nm for the other area. It is should be emphasized that the present analysis of lattice distortions is immediately applicable to the other semiconductors, such as Si, SiGe or GaAs layers, without assuming any crystal system.     

Modeling of current-voltage characteristics for dual-gate amorphous silicon thin-film transistors considering deep Gaussian density-of-state distribution

Considering combination of the deep Gaussian and tail exponential distribution of DOS (density of states) instead of double exponentials empirically, a physics-based approximation has been developed to describe the behavior of the surface and centric potential as a function of applied voltage for DG a-Si:H TFT (amorphous silicon thin film transistor with dual gate). The resulting scheme provides a novel method for quickly evaluation of the inter-related potentials and is proved to offer better computational efficiency than other numerical alternatives. Based on these potentials, a compact drain current model accounting for the interaction factor has been proposed that followed. We show what parameters are truly required for accurately describing the I-V characteristic of DG a-Si:H TFT and just how qualitatively these parameters affect TFTs current. Model derivation also demonstrated an intuitive physical explanation for the gate-voltage dependent mobility as usually observed experimentally in these devices. Terms of potentials and current calculation are successively verified by comparison with numerical and the published experimental data.     

水体非线性伏安特性的研究

为了研究水体的伏安特性,基于实验室环境,设计了相应的测量电路,得到一组不同电压下的水体电阻值数据;通过分析比较,发现水体两端所受的电压越大,其电阻值则越小这一现象；同时利用matlab对所得到的数据进行polyfit函数拟合,得到一定外部电源电压下的水体电阻值与其两端所受电压之间的关系式,从而得出水体具有非线性的伏安特性这一结论.     

Characteristics and fabrication of nanohole array on InP semiconductor substrate using nanoporous alumina

Uniform arrays of nano-sized pore produced in porous alumina were transferred into InP substrates by inductively coupled plasma reactive ion etching (ICP-RIE). We observed a significant enhancement in the light output from InP substrate with nanohole arrays on the surface. Photoluminescence intensity of triangular arrays of air cylinders on InP substrate showed an enhancement up to 3 times compared with that from a raw InP substrate without such structure. The ICP-RIE technique using nanoporous alumina mask can be used as a prospective method in the fabrication of nanostructure materials for increasing the light output from semiconductor light emitting devices.     

Design of InP DHBT power amplifiers at millimeter-wave frequencies using interstage matched cascode technique

In this paper, the design of InP DHBT based millimeter-wave(mm-wave) power amplifiers(PAs) using an interstage matched cascode technique is presented. The output power of a traditional cascode is limited by the early saturation of the common-base(CB) device. The interstage matched cascode can be employed to improve the power handling ability through optimizing the input impedance of the CB device. The minimized power mismatch between the CB and the common-emitter(CE) devices results in an improved saturated output power. To demonstrate the technique for power amplifier designs at mm-wave frequencies, a single-branch cascode based PA using single-finger devices and a two-way combined based PA using three-finger devices are fabricated. The single-branch design shows a measured power gain of 9.2 dB and a saturated output power of 12.3 dBm at 67.2 GHz and the two-way combined design shows a power gain of 9.5 dB with a saturated output power of 18.6 dBm at 72.6 GHz.     

Simulation of current-voltage characteristics of a ferroelectric field-effect transistor

Current-voltage (I-V) characteristics of an all-perovskite ferroelectric-semiconductor field-effect transistor (FET) were simulated. The modeling is based on an analysis of an experimental hysteresis loop of a metal-ferroelectric-metal structure. The charge in the semiconductor, electric fields in the semiconductor and ferroelectric (FE), and FE polarization at the FE-semiconductor interface are calculated at a given semiconductor surface potential. The Poisson equation is solved numerically across the FE thickness. The semiconductor surface potential, semiconductor charge, FE polarization, electric field and voltage drop in the FE are calculated as functions of the applied voltage. By using appropriate semiconductor thickness and built-in voltage between the FE and the gate, it is possible to provide a remanent polarization necessary for the opening and blocking of the FET channel in the ascending and descending portions of the hysteresis loop, respectively. The I-V characteristics and the voltage drop along the FET channel are calculated and analyzed for both polarities of the drain bias. The results make it possible to predict I-V characteristics of an all-perovskite ferroelectric FET.     

The characteristics of Zn-doped InP using spin-on dopant as a diffusion source

Zn diffusion into InP was carried out ex-situ using a spin-on dopant as a diffusion source. The characteristics of Zn-doped InP are analyzed using low-temperature photoluminescence (PL), differential Hall measurement, and secondary ion mass spectrometry (SIMS). Dopant activation of Zn is close to 100% using this method. Band-to-acceptor (B-A) transition peak is dominant in PL, which is a characteristic usually found in in-situ doping. This evidence along with an activation energy of 0.5 eV show that the diffusion is substitutional rather than interstitial.     

1.55 μm InGaAsP/InP laser buried in a high-resistivity epitaxiallayer on a semi-insulating InP substrate

A buried heterostructure (BH) 1.55 μm laser embedded in a high resistivity epitaxial layer on a semi-insulating substrate is described. This device has a planar surface and both a p- and an n-type electrode on the same side, facilitating integration of electronic devices. Its threshold current is typically 9 mA. Its small signal 3 dB modulation bandwidth was 14 GHz due to the reduction of device resistance and capacitance. No degradation was observed in an aging test at 50°C even after more than 3000 h     

Modeling of strained CMOS on disposable SiGe dots: Shape impacts on electrical/thermal characteristics

We proposed a new non-planar disposable SiGe dot (d-Dot) MOSFET based on Si-on-nothing technology. The new device concepts’ relies on self-assembled single-crystalline d-Dot. The d-Dot MOSFET is prone to a particularly high strain/stress from the underlaying SiGe 3D islands. We show that more than 50% higher mobilities of electrons can be obtained as indicated by 3D simulations performed throughout the entire fabrication process. Then, fully-depleted SOI MOSFET and d-Dot MOSFET are compared in term of short channel effects, parasitic capacitance effects and self-heating effects.