The effect of interface states, excess capacitance and series resistance in the Al/SiO2/p-Si Schottky diodes

The current-voltage (I-V) characteristics of Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) Schottky diodes were measured at room temperature. In addition the capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are studied at frequency range of 10 kHz-1 MHz. The higher value of ideality factor of 3.25 was attributed to the presence of an interfacial insulator layer between metal and semiconductor and the high density of interface states localized at Si/SiO₂ interface. The density of interface states (N_ss) distribution profile as a function of (E_ss − E_v) was extracted from the forward bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_e) at room temperature for the Schottky diode on the order of ≅4 × 10¹³ eV⁻¹ cm⁻²_. These high values of N_ss were responsible for the non-ideal behaviour of I-V and C-V characteristics. Frequency dispersion in C-V and G-V can be interpreted only in terms of interface states. The N_ss can follow the ac signal especially at low frequencies and yield an excess capacitance. Experimental results show that the I-V, C-V and G-V characteristics of SD are affected not only in N_ss but also in series resistance (R_s), and the location of N_ss and R_s has a significant on electrical characteristics of Schottky diodes.     

Inhomogeneities in 130 MeV Au ion irradiated Au/n-Si (1 0 0) Schottky structure

The electrical characteristics of Au/n-Si (1 0 0) Schottky rectifier have been studied in a wide irradiation fluence range using conventional current-voltage (I-V) and capacitance-voltage (C-V) measurements. The I-V characteristics showed an abnormal increase in forward current at low voltage. The device shows a bend in forward I-V and reverses bias C-V characteristics due to extra current, suggesting that there are two independent contributions to thermionic current, corresponding to two levels of the Schottky barrier. It is shown that the excess current at low voltage can be explained by taking into account the role of heavy ion irradiation induced defects at the metal semiconductor interface.     

Temperature dependent transport properties of CuInSe2-ZnO heterostructure solar Cell

Experimental study of dc and ac transport properties of CuInSe₂/ZnO heterostructure is presented. The current-voltage (I-V) and frequency dependent capacitance (C-f) characteristics of CuInSe₂/ZnO heterostructure were investigated in the temperature range 160-393 K. The heterostructure showed non-ideal behavior of I-V characteristics with an ideality factor of 3.0 at room temperature. Temperature dependent dc conductivity studies exhibited Arrhenius type behavior and revealed the presence of trap level. The C⁻²-V plot measured at frequency 50 kHz had shown non-linear behavior. An increase in capacitance with temperature was observed. The capacitance-frequency characteristics exhibited a transition between low frequency and the high frequency capacitance. As the temperature was lowered the transition occurred at lower frequencies. The frequency and temperature dependent device capacitance had shown a defect state having activation energy of 108 meV.     

Capacitance–voltage and conductance–voltage characteristics of Ag/n-CdO/p-Si MIS structure prepared by sol–gel method

The frequency dependent electrical properties of Ag/n-CdO/p-Si structure has been investigated using capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics in the frequency range 10 kHz–1 MHz in the room temperature. The increase in capacitance at lower frequencies is observed as a signature of interface states. The presence of the interfaces states (N_SS) is also evidenced as a peak in the capacitance–frequency characteristics. Furthermore, the voltage and frequency dependence of series resistance were calculated from the C–V and G/ω–V measurements and plotted as functions of voltage and frequency. The distribution profile of R_S–V gives a peak in the depletion region at low frequencies and disappears with increasing frequencies. The values of interface state densities and series resistance from capacitance–voltage-frequency (C–V-f) and conductance–voltage-frequency (G/ω–V-f) measurements were obtained in the ranges of 1.44×10¹⁶–7.59×10¹² cm^?2 eV^?1 and 341.49–8.77 Ω, respectively. The obtained results show that the C–V-f and G/ω–V-f characteristics confirm that the interface states density (N_SS) and series resistance (R_S) of the diode are important parameters that strongly influence the electrical parameters in Ag/n-CdO/p-Si structures.     

Current conduction mechanism in Al/p-Si Schottky barrier diodes with native insulator layer at low temperatures

The forward bias current-voltage (I-V) characteristics of Al/p-Si (MS) Schottky diodes with native insulator layer were measured in the temperature range of 80-300 K. The obtained zero bias barrier height Φ_B0(I-V), ideality factor (n) and series resistance (R_s) determined by using thermionic emission (TE) mechanism show strong temperature dependence. There is a linear correlation between the Φ_B0(I-V) and n because of the inhomogeneties in the barrier heights (BHs). Calculated values from temperature dependent I-V data reveal an unusual behaviour such that the Φ_B0 decreases, as the n and R_s values are increasing with decreasing absolute temperature, and these changes are more pronounced especially at low temperatures. Such temperature dependence of BH is contradictory with the reported negative temperature coefficient of the barrier height. In order to explain this behaviour we have reported a modification in the expression reverse saturation current I_o including the n and the tunnelling factor (αΧ^1/2δ) estimated to be 15.5. Therefore, corrected effective barrier height Φ_bef.(I-V) versus temperature has a negative temperature coefficients (α = −2.66 × 10⁻⁴ eV/K) and it is in good agreement with negative temperature coefficients (α = −4.73 × 10⁻⁴ eV/K) of Si band gap. In addition, the temperature dependent energy distribution of interface states density N_ss profiles was obtained from the forward bias I-V measurements by taking into account the bias dependence of the Φ_e and n. The forward bias I-V characteristics confirm that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that the current conduction mechanism of MS Schottky diodes.     

The effect of series resistance and interface states on the frequency dependent C–V and G/w–V characteristics of Al/perylene/p-Si MPS type Schottky barrier diodes

The capacitance–voltage–frequency (C–V–f) and conductance–voltage–frequency (G/w–V–f) characteristics of Al/perylene/p-Si Schottky barrier diodes (SBDs) fabricated with spin coating system have been investigated in the frequency range of 30 kHz–2 MHz at room temperature. In order to elucidate the electrical characteristics of SBDs with perylene interface, the voltage and frequency dependent series resistance (R_s), frequency dependent density distribution profile of interface state (N_ss) were obtained. The measurements of C and G/w were found to be strongly dependent on bias voltage and frequency for Al/perylene/p-Si SBDs. For each frequency, the R_s–V plot gives a peak, decreasing with increasing frequencies. Also, it has been shown that the interface states density exponentially decreases with increasing frequency. The C–V–f and G/w–V–f characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in metal/polymer/semiconductor (MPS) structure.     

Current transport mechanism in Al/Si3N4/p-Si (MIS) Schottky barrier diodes at low temperatures

The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of metal-insulator-semiconductor (Al/Si₃N₄/p-Si) Schottky barrier diodes (SBDs) were measured in the temperature range of 80-300 K. By using the thermionic emission (TE) theory, the zero-bias barrier height Φ_B0 calculated from I-V characteristics was found to increase with increasing temperature. Such temperature dependence is an obvious disagreement with the negative temperature coefficient of the barrier height calculated from C-V characteristics. Also, the ideality factor decreases with increasing temperature, and especially the activation energy plot is nonlinear at low temperatures. Such behaviour is attributed to Schottky barrier inhomogeneties by assuming a Gaussian distribution of barrier heights (BHs) at interface. We attempted to draw a Φ_B0 versus q/2kT plot to obtain evidence of a Gaussian distribution of the BHs, and the values of Φ_Bo = 0.826 eV and α_o = 0.091 V for the mean barrier height and standard deviation at zero-bias, respectively, have been obtained from this plot. Thus, a modified ln(I_o/T²) − q²σ_o²/2(kT)² versus q/kT plot gives Φ_B0 and Richardson constant A^* as 0.820 eV and 30.273 A/cm² K², respectively, without using the temperature coefficient of the barrier height. This value of the Richardson constant 30.273 A/cm² K² is very close to the theoretical value of 32 A/cm² K² for p-type Si. Hence, it has been concluded that the temperature dependence of the forward I-V characteristics of the Al/Si₃N₄/p-Si Schottky barrier diodes can be successfully explained on the basis of TE mechanism with a Gaussian distribution of the barrier heights. In addition, the temperature dependence of energy distribution of interface state density (N_SS) profiles was determined from the forward I-V measurements by taking into account the bias dependence of the effective barrier height and ideality factor.     

Comparison of electrical parameters of Zn/p-Si and Sn/p-Si Schottky barrier diodes

In this study, current-voltage (I-V) and capacitance-voltage (C-V) characteristics of metal-semiconductor (MS) Zn/p-Si and Sn/p-Si Schottky diodes, with high resistivity silicon structures, are investigated. The parameters of series resistance (R_S), the ideality factor (n) and the barrier height (Φ_b) are determined by performing different plots from the forward bias current-voltage (I-V) and reverse bias capacitance-voltage (C-V) characteristics. Thus, the barrier heights (Φ_b) for the Si Schottky diodes obtained between 0.725 and 1.051 eV, the ideality factor (n) between 1.043 and 1.309, and the series resistance (R_S) between 12.594 and 12.950 kΩ. The energy distribution of interface states density was determined from the forward bias I-V characteristics by taking into account the bias dependence of the effective barrier height. It was concluded that the density of interface states in the considered energy range are in close agreement with each other values obtained for Zn/p-Si and Sn/p-Si Schottky diodes.     

Electrical and dielectric properties of Al/HfO2/p-Si MOS device at high temperatures

The temperature dependence of capacitance–voltage (C–V) and conductance–voltage (G/w–V) characteristics of Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) device has been investigated by considering the effect of series resistance (R_s) and interface state density (N_ss) over the temperature range of 300–400 K. The C–V and G/w–V characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in MOS device. It is found that in the presence of series resistance, the forward bias C–V plots exhibits a peak, and its position shifts towards lower voltages with increasing temperature. The density of N_ss, depending on the temperature, was determined from the (C–V) and (G/w–V) data using the Hill–Coleman Method. Also, the temperature dependence of dielectric properties at different fixed frequencies over the temperature range of 300–400 K was investigated. In addition, the electric modulus formalisms were employed to understand the relaxation mechanism of the Al/HfO₂/p-Si structure.     

The effect of gamma irradiation on electrical and dielectric properties of Al-TiW-Pd2Si/n-Si Schottky diode at room temperature

The effects of ⁶⁰Co (γ-ray) irradiation on the electrical and dielectric properties of Al-TiW-Pd₂Si/n-Si Schottky diodes (SDs) have been investigated by using capacitance-voltage (C-V) and conductance-voltage (G/ω-V) measurements at room temperature and 500 KHz. The corrected capacitance and conductance values were obtained by eliminating the effect of series resistance (R_s) on the measured capacitance (C_m) and conductance (G_m) values. The high-low frequency capacitance (CHF-CLF) method given in [12] as N_ss = (1/qA) [((1/C_LF) − (1/C_ox))⁻¹ −  ((1/C_HF) − (1/C_ox))⁻¹] was successfully adapted to the before-after irradiation capacitance given in this report as N_ss = (1/qA) [((1/C_bef) − (1/C_ox))⁻¹ − ((1/C_after) − (1/C_ox))⁻¹] for the analyzing the density of interface states. The N_ss-V plots give a distinct peak corresponding to localized interface states regions at metal and semiconductor interface. The experimental values of the ac electrical conductivity (σ_ac), the real (M′) and imaginary (M″) parts of the electrical modulus were found to be strong functions of radiation and applied bias voltage, especially in the depletion and accumulation regions. The changes in the dielectric properties in the depletion and accumulation regions stem especially from the restructuring and reordering of the charges at interface states and surface polarization whereas those in the accumulation region are caused by series resistance effect.     

Electrical characteristics of polycrystalline Si layers embedded into high-k Al2O3 gate layers

The electrical characteristics of polycrystalline Si (poly Si) layers embedded into high-k Al₂O₃ (alumina) gate layers are investigated in this work. The capacitance versus voltage (C-V) curves obtained from the metal-alumina-polysilicon-alumina-silicon (MASAS) capacitors exhibit significant threshold voltage shifts, and the width of their hysteresis window is dependent on the range of the voltage sweep. The counterclockwise hysteresis observed in the C-V curves indicates that electrons originating from the p-type Si substrate in the inversion condition are trapped in the floating gate layer consisting of the poly Si layer present between the top and bottom Al₂O₃ layers in the MASAS capacitor. Also, current versus voltage (I-V) measurements are performed to examine the electrical characteristics of the fabricated capacitors. The I-V measurements reveal that our MASAS capacitors show a very low leakage current density, compared to the previously reported results.     

Temperature dependence of the current-voltage characteristics of the Al/Rhodamine-101/p-Si(1 0 0) contacts

The current-voltage (I-V) characteristics of Al/Rhodamine-101/p-Si/Al contacts have been measured at temperatures ranging from 280 to 400 K at 20 K intervals. A barrier height (BH) value of 0.817 eV for the Al/Rh101/p-Si/Al contact was obtained at the room temperature that is significantly larger than the value of 0.58 eV of the conventional Al/p-Si Schottky diode. While the barrier height Φ_b0 decreases the ideality factors (n) become larger with lowering temperature. The high values of n depending on the sample temperature may be ascribed to decrease of the exponentially increase rate in current due to space-charge injection into Rh101 thin film at higher voltage. Therefore, at all temperatures, it has been seen that the I-V characteristics show three different regions, the ohmic behavior at low voltages, and the space charge limited current with an exponential distribution of traps at high voltages.     

Correlation between barrier heights and ideality factors of Cd/n-Si and Cd/p-Si Schottky barrier diodes

Our goal is to experimentally investigate whether or not the effective Schottky barrier heights (SBHs) and ideality factors obtained from the current-voltage (I-V) and capacitance-voltage (C-V) characteristics differ from diode to diode even if the samples were identically prepared. For this purpose, we prepared Cd/n-Si (33 dots) and Cd/p-Si (15 dots) diodes. The SBH for the Cd/n-Si diodes ranged from 0.701 to 0.605 eV, and ideality factor n from 1.913 to 1.213. Φ_b value for the Cd/p-Si diodes ranged from 0.688 to 0.730 eV, and ideality factor n value from 1.473 to 1.040. The experimental SBH distributions obtained from the C⁻²-V and I-V characteristics were fitted by a Gaussian function and their mean SBH values were calculated. Furthermore, the laterally homogeneous barrier heights were also computed from the extrapolation of the linear plot of experimental barrier heights versus ideality factors.     

Molecular control over Ag/p-Si diode by organic layer

Electrical transport properties of Ag metal-fluorescein sodium salt (FSS) organic layer-silicon junction have been investigated. The current-voltage (I-V) characteristics of the diode show rectifying behavior consistent with a potential barrier formed at the interface. The diode indicates a non-ideal I-V behavior with an ideality factor higher than unity. The ideality factor of the Ag/FSS/p-Si diode decreases with increasing temperature and the barrier height increases with increasing temperature. The barrier height (φ_b=0.98 eV) obtained from the capacitance-voltage (C-V) curve is higher than barrier height (φ_b=0.72 eV) derived from the I-V measurements. The barrier height of the Ag/FSS/p-Si Schottky diode at the room temperature is significantly larger than that of the Ag/p-Si Schottky diode. It is evaluated that the FSS organic layer controls electrical charge transport properties of Ag/p-Si diode by excluding effects of the SiO₂ residual oxides on the hybrid diode.     

Negative capacitance of ZnGa2Se4/Si nano-heterojunction diode

The negative capacitance (NC) behavior in p-ZnGa₂Se₄/n-Si nano-crystalline HJD was characterized by admittance-voltage method. The C–V, G–V and R _s –V for the studied diode were analysed in the frequency range of 1–5 MHz and in the temperature range of 303–423 K. The capacitance and conductance plots were interpreted in terms of interface states and series resistance. The C–V and G/ω–V plots exhibit a pounced peak due to the interface states and the series resistance effects. The negative capacitance behavior in the studied diode can be explained in terms of the transient currents.     

Effects of ageing on the electrical characteristics of Cd/CdS/n-Si/Au–Sb structure deposited by SILAR method

Cd/CdS/n-Si/Au–Sb structure has been fabricated by the Successive Ionic Layer Adsorption and Reaction (SILAR) method and the influence of the time dependent or ageing on the characteristic parameters are examined. The current–voltage (I–V), capacitance–voltage (C–V) and capacitance–frequency (C–f) characteristics of the structure have been measured immediately, 1, 3, 5, 15, 30, 45, 60, 75, 90, 105, 120, 135, 150 and 165 days after fabrication of the structure. The characteristic parameters of the structure such as barrier height, ideality factor, series resistance are calculated from the I–V measurements and the barrier height, carrier concentration values are calculated from reverse bias C^?2–V measurements at 500 kHz and room temperature. Furthermore, the density distribution and time constant of the interface states have been calculated from the C–f measurements using the Schottky Capacitance Spectroscopy method as a function of ageing time. It has been seen that the changes of characteristic parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au–Sb structure have lightly changed with increasing ageing time. At the same time, the rectifying ratio of the device increases with ageing time. It can be clearly said that the I–V characteristics of device get better with time.     

Effect of series resistance and interface states on the I-V, C-V and G/ω-V characteristics in Au/Bi-doped polyvinyl alcohol (PVA)/n-Si Schottky barrier diodes at room temperature

The forward and reverse bias current-voltage (I-V), capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the Au/PVA (Bi-doped)/n-Si Schottky barrier diodes (SBDs) have been investigated at room temperature by taking the interface states (N_ss) and series resistance (R_s) effects into account. The voltage dependent profiles of resistance (R_i) were obtained from both the I-V and C/G-V measurements by using Ohm’s Law and Nicollian methods. The obtained values of R_i with agreement each other especially at sufficiently high bias voltages which correspond the value of R_s of the diode. Therefore, the energy density distribution profile of N_ss was obtained from the forward bias I-V data taking the bias dependence of the effective barrier height (BH) Φ_e and R_s into account. The high value of ideality factor (n) was attributed to high density of N_ss and interfacial polymer layer at metal/semiconductor (M/S) interface. In order to examine the frequency dependence of some of the electrical parameters such as doping donor concentration (N_D), Φ_e, R_s and N_ss values, C-V and G/ω-V measurements of the diode were performed at room temperature in the frequency range of 50 kHz-5 MHz. Experimental results confirmed that the N_ss, R_s and interfacial layer are important parameters that influence electrical characteristics of SBD.     

Electric characterization of GaAs deposited on porous silicon by electrodeposition technique

GaAs thin films were synthesized on porous Si substrate by the electrodeposition technique. The X-ray diffraction studies showed that the as-grown films were crystallised in mixed phase nature orthorhombic and cubic of GaAs. The GaAs film was then electrically characterized using current-voltage (I-V) and capacitance-voltage (C-V) techniques by the way of Al/GaAs Shottky junctions. The electric analysis allowed us to determine the n factor and the barrier height Ф_b0 parameters of Al/GaAs Schottky junctions. The (C-V) characteristics were recorded at frequency signal 1 MHz in order to identify the effect of the surface states on the behaviour of the capacitance of the device.     

Effect of the oxidation process on SiO2/4H-SiC interface electrical characteristics

In this work we have compared the SiO₂/SiC interface electrical characteristics for three different oxidations processes (dry oxygen, water-containing oxygen and water-containing nitrogen atmospheres). MOS structures were fabricated on 8° off-axis 4H-SiC(0 0 0 1) n- and p-type epi-wafers. Electrical characteristics were obtained by I-V measurements, high-frequency capacitance-voltage (C-V) and ac conductance (G-ω) methods. Comparing the results, one observes remarkable differences between samples which underwent different oxidation routes. Among the MOS structures analyzed, the sample which underwent wet oxidation with oxygen as carrier gas presented the higher dielectric strength and lower values of interface states density.     

The origin of negative capacitance in Au/n-GaAs Schottky barrier diodes (SBDs) prepared by photolithography technique in the wide frequency range

Capacitance–voltage (C–V) and conductance–voltage (G/ω–V) measurements of the Au/n-GaAs Schottky barrier diodes (SBDs) in the wide frequency range of 10 kHz–10 MHz at room temperature were carried out in order to evaluate the reason of negative capacitance (NC). Experimental results show that C and G/ω are strong functions of frequency and bias voltage especially in the accumulation region. NC behavior was observed in the C–V plot for each frequency and the magnitude of absolute value of C increases with decreasing frequency in the forward bias region. Contrary to C, G/ω increases with decreasing frequency positively in this region. NC behavior may be explained by considering the loss of interface charges at occupied states below Fermi level due to impact ionization processes. Such behavior of the C and G/ω values can also be attributed to the increase in the polarization especially at low frequencies and the introduction of more carriers in the structure. The values of R_s decrease exponentially with increasing frequency according to literature. In addition, the values of C and G/ω at 1 MHz were corrected to obtain the real diode capacitance by taking the effect of R_s into account.