High-speed interconnects with underlayer orthogonal metal grids

On-chip high-speed interconnects with underlayer orthogonal metal grids, including grid-backed lines (GBLs) and grid-backed coplanar waveguides (GBCPWs), are characterized through s-parameter measurements. For GBL test structures, the presence of underlayer metal grids reduces dispersion by a factor of 4 while the local speed of light decreases by a factor of 2 in comparison to those of conventional microstrip lines. The dispersion reduction comes from suppressing higher order modes; the local speed of light reduction comes from a longer current return path. These characteristics are beneficial for compact CMOS analog circuit designs. Losses caused by substrate and conductor lines are restrained by shielding the substrate and by involving weaker electric fields. Resonance at a frequency characterized by that of a patch antenna was observed and needs to be considered in high-speed circuit designs. The grids have weaker effects in the case of CPWs, where the side ground plate effects are significant. A signal transmission example shows that dispersion and frequency-dependent losses are important in determining the signal rise edge. Semi-empirical distributed resistance-inductance-capacitance-conductance (RLCG) equivalent circuit models are constructed for the interconnects below the resonant frequencies.     

三层金属布线的SOG隔离工艺开发

摘要: SOG平坦化技术是一种采用液态介质材料填充CMOS后段布线工艺中金属间隙的工艺技术,它使得硅片表面平坦化,物理特性上它和PECVD淀积SiO2类似,二者具有相似的电特性,SOG材料的介电常数低,具有良好的绝缘特性,是一种常用的金属层间隔离材料。但SOG材料和金属间的粘附性差、容易开裂等问题都阻碍了SOG技术作为多层金属层间介质的应用,特别是在大生产工艺上。本文采用首先CVD淀积一层薄SiO2,接着进行SOG涂敷固化和反腐工艺,最后再淀积顶层SiO2,形成三明治介质机构,这样有利于提高粘附性、防止开裂和孔中毒等问题,同时用电扫描显微镜对采用此结构的三层布线工艺进行纵向剖面分析。这种结构在CMOS三层布线工艺中已成功开发,并在0.5m CMOS DPTM批量生产中得到应用和验证。     

Design of metal interconnects for stretchable electronic circuits

The trend of microelectronic products in the textile or medical field is toward higher functionality, miniaturization, application of new materials and a necessity for deformable electronic circuits for improving the comfort control. In this work, the design of flexible and stretchable interconnections is presented. These interconnections are done by embedding sinuous electroplated metallic wires in a stretchable substrate material. A silicone material was chosen as substrate because of its low stiffness and high elongation before break. Common metal conductors used in the electronic industry have very limited elastic ranges; therefore a metallization design is crucial to allow stretchability of the conductors going up to 100%.Different configurations were simulated and compared among them and based on these results, a horseshoe like shape was suggested. This design allows a large deformation with the minimum stress concentration. Moreover, the damage in the metal is significantly reduced by applying narrow metallization schemes. In this way, each conductor track has been split in four parallel lines of 15 μm and 15 μm space in order to improve the mechanical performance without limiting the electrical characteristics.     

Development of spin-on-glass process for triple metal interconnects

Spin-on-glass(SOG),an interlayer dielectric material applied in liquid form to fill narrow gaps in the sub-dielectric surface and thus conducive to planarization,is an alternative to silicon dioxide(SiO_2) deposited using PECVD processes.However,its inability to adhere to metal and problems such as cracking prevent the easy application of SOG technology to provide an interlayer dielectric in multilevel metal interconnect circuits,particularly in university processing labs.This paper will show that a thin...     

ATCS: Advanced Train Control System radio data link designconsiderations

The American Association of Railroads (AAR) and the Association of Canadian Railroads (ACR) jointly initiated an implementation study of the Advanced Train Control System (ATCS) to improve the efficiency and economics of railroad operations. The data link between locomotives and the dispatcher is identified as a vital link within ATCS. The design of this link includes considerations on modulation, data rates, protocol, access scheme, forward error control, and their impact on spectral needs. The steps taken toward specifying ATCS radio-link design parameters to meet operational requirements of railroads are described. Extensive computer simulations to evaluate suitability of the chosen system parameters such as data rate, access scheme, and coding were made under some realistic mobile channel conditions. Results of this design exercise are summarized     

Deep linking: an ethical and legal analysis

Deep linking, the practice of linking to a subsidiary page rather than the home page of another organization's Web site, is the subject of considerable controversy. In several recent lawsuits, plaintiffs have alleged violations of copyright, trademark, and commercial laws. I review the legal and ethical issues regarding deep linking and comment on how the ethical conflict between rights and utility motivates the controversy. I conclude that protecting site owners' rights to control deep linking to their sites is a stronger value than enhancing the utility of the Web for users by allowing completely unrestricted deep linking. Finally, I recommend a collection of resources for Web developers interested in staying current with the evolving controversy     

Crosstalk analysis of simultaneously switching interconnects

This article focusses on the waveform analysis and crosstalk peak estimation at far-end of victim line for simultaneously switching inputs with resistive drivers. A low loss coupled transmission line-model of interconnect is used for analytical purpose. Noise peaks are estimated for the conditions when inputs to two coupled interconnects are switching in-phase and out-of-phase. Waveforms are analysed in general with homogeneous and non-homogeneous drivers for unipolar inputs. The driver is modelled as linear resistance. Comparison of the analytical results with simulation programme with integrated circuit emphasis (SPICE)-extracted results shows that the error involved is less than 2% and 5% for in-phase and out-of-phase switching, respectively. The comparisons of analytically obtained results with SPICE simulations show that the proposed model captures noise peaks, their timings and waveform shape for all switching conditions with an average error of less than 4%.     

Analysis of thermal stresses in metal interconnects with multilevel structures

The evolution of thermal stresses in aluminum interconnects was analyzed numerically. Particular attention was devoted to the effects of multilevel arrangement, which have been largely ignored in past studies. Two-dimensional models based on long metal lines with different aspect ratios and cross-sectional arrangements were employed. The metallization, taken to include thin refractory layers sandwiching the aluminum conductor, was embedded within silicon oxide dielectric on top of the silicon substrate. A thermal cooling process was simulated by recourse to the finite element method. It was found that the incorporation of refractory layers increases the stress in aluminum lines. The line aspect ratio, rather than the multilevel nature, plays the most important role in affecting the thermal stress. Issues related to interconnect stress modeling and reliability implications are discussed.     

Design and performance of thin metal film interconnects for skin-like electronic circuits

We prepare stretchable electrical conductors of 25-nm-thick gold films on elastomeric substrates prestretched by 15%. When the substrates relax from the prestretch, the gold stripes form surface waves with /spl sim/8.4-/spl mu/m wavelength and /spl sim/1.2-/spl mu/m amplitude. When the strain is cycled between 0 and 15%, both the wave pattern and the electrical resistance of the gold stripes change in reproducible cycles. Such repeatedly stretchable metallization can serve as interconnects for skin-like, conformal, and electroactive polymer circuits.     

Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

The effects of defects on the early failure of metal interconnects

A method that predicts the effect of particular defects on the failure rate of metal interconnections in semiconductor integrated circuits due to electromigration is presented. The defects of interest are missing material that reduces the effective cross section of the conductor at the point of the defect. Reliability measures for the conductor are computed from a given defect distribution. These defects appreciably increase conductor failure rate during early life but have little effect on median life for linewidths above 1 μm. However, for defect densities typically encountered in current semiconductor manufacturing environments a rapid decrease in median life is predicted for conductors less than 0.30 μm wide. This result extends the practical data for submicron conductors. Poorer median life as well as poorer yield due to these defects will ultimately limit the trend toward narrower linewidths unless a way is found to overcome this problem     

Delay analysis of buffer inserted sub-threshold interconnects

In this paper, an analysis of interconnect delay minimization by CMOS buffer insertion in sub-threshold regime is presented. Analytical expressions are developed to calculate the total delay and optimum number of buffers required for delay minimization in sub-threshold interconnects. Considering delay minimization by buffer insertion, the effects of voltage-scaling on the delay and optimum number of buffers have been analyzed. It is demonstrated that voltage scaling in sub-threshold regime reduces the number of buffers required to attain the minimum delay. This is one more advantage of voltage-scaling in addition to the usual reduction in power dissipation, in the sense that lesser silicon area is consumed. For a wide variety of typical interconnect loads, analytically obtained results are in good agreement with SPICE extracted results for most of the cases more than 90 %. Finally, the variability analysis of sub-threshold interconnects is investigated using Monte Carlo analysis.     

Creation mechanism of metal depression in sputtering process for aluminum interconnects

For the aluminum (Al) metal line device fabricated by sputtering process, one of the frequently seen and well-known defects was metal depression. In this paper, several experiments were performed which consisted in varying the temperature, Ar gas flow rate, thickness, and stabilization time to eliminate this defect and to find the origination of the metal depression for below 0.13 μm technology. The metal depression was significantly related to the temperature, where the less metal depression was observed in relatively low temperature. The Ar gas flow rate did not influence the creation of the metal depression. The off-state ESC also showed the good surface morphology without the metal depression. The metal depression showed the inverse tendency to the thickness of Al film, however there is a limit to the thick Al film. The stabilization time after Al deposition was a very important factor for the metal depression. The sufficient stabilization time eliminated the metal depression through the resistance ability against the thermal stress.     

金属互连线电迁移过程中的高温蠕变行为研究

基于ABAQUS有限元分析软件,对金属互连线的蠕变行为进行了研究,获取了高温下的蠕变应力分布云图,并分析了不同温度、不同升温速率等参数对铝硅合金互连线蠕变行为的影响规律。结果表明:在温度载荷作用下,铝硅合金互连线的蠕变应力在互连线狭窄部位即尺寸突变的部位,呈现明显的应力集中现象;随着温度载荷的升高,互连线内部的蠕变应力值逐渐增大,且二者之间的关系近似为一条直线;在其他条件均相同的情况下,升温速率越快,互连线内部应力达到最大值所用的时间就越短,导致互连线承受高应力值的时间就越长,从而会加速部件的失效。     

深亚微米多层互连的温度分布特性分析

本文从热扩散方程出发,推导了简单互连的温度分布解析表达式,采用65nm工艺参数,详细讨论了热扩散长度和介质层厚度对互连温度分布的影响;进一步给出了复杂多层互连的温度分布解析表达式并用于其特性模拟,结果显示全局互连的温升远大于半全局互连和局部互连的温升。     

Random vibration analysis of 3-Arc-Fan compliant interconnects

Microelectronic packaging compliant interconnects offer increased reliability when compared to traditional rigid solder ball interconnects. These interconnects are subject to various forms of mechanical damage including thermal cycle fatigue, drop impact shock, and vibration environments that often lead to mechanical or electrical failure. Second-level compliant interconnects seek to alleviate this issue by decoupling the substrate and board, facilitating independent deformation while experiencing lower stresses and strains. In order to develop compliant interconnects as an effective alternative to rigid solder balls, various design optimization, thermal cycling test, and drop impact studies have been performed. However, the area of vibration characterization and analysis is lacking for microelectronic packaging and nonexistent for compliant interconnects. Therefore, this paper will present a complete vibration analysis of a particular multi-path compliant interconnect design, the 3-Arc-Fan compliant interconnect. This design features three electroplated copper arcuate beams that provide a spring-like effect to increase compliance and mechanical reliability. Experimental vibration characterization was performed and used to validate the simulation model. Following which a random vibration analysis method wais established, and the samples were tested at various conditions. Finally, both experimental and simulation results were integrated to develop a preliminary fatigue life prediction model to demonstrate the increased reliability.     

Crosstalk bandwidth and stability analysis in graphene nanoribbon interconnects

Based on transmission line modeling (TLM), and using the Nichols chart, we present a bandwidth and stability analysis, together with step time responses, for coupled multilayer graphene nanoribbon (MLGNR) interconnects that is inquired for the first time. In this analysis, the dependence of the degree of crosstalk relative stability for coupled MLGNR interconnects comprising of both capacitive and mutual-inductive couplings between adjacent MLGNR has been acquired. The obtained results show that with increasing the length or decreasing the width of the MLGNRs, the stability in near-end output increases. While, any increase in the length or width of MLGNRs, decrease the stability of far-end output. Also, by increasing capacitive coupling or decreasing inductive coupling, the near-end output becomes more stable, and the far-end output becomes less stable. Moreover, any increase in the length or capacitive coupling, decreases the bandwidth, whereas any increase in the width or inductive coupling, increases the bandwidth. Finally, transient simulations with Advanced Design System (ADS) show that the model has an excellent accuracy.     

Characteristic analysis of coupled HTS interconnects withtwo-dimensional FDTD

In this work, the frequency-dependent RLGC parameters of high-speed coupled high T_c superconductor (HTS) interconnects are extracted with a two-dimensional (2-D) FDTD algorithm. The response signals of an HTS interconnect circuit and a normal Al interconnect circuit are simulated and compared, showing that not only the signal dispersion, delay, and magnitude decay of HTS interconnects are smaller than that of Al interconnects, the crosstalk of HTS interconnects is much smaller, too     

Electromagnetic analysis of multiconductor losses and dispersion in high-speed interconnects

A self-consistent electromagnetic analysis of multiconductor transmission lines is presented for high-speed, high-density MMIC's and VLSI interconnects. In contrast to classical approach, this analysis handles the multiconductor as normal dielectric with high conductivity in electromagnetic simulation. Therefore, dispersion and loss effects can exactly be described in this model. Examples of interconnect circuits with up to four conductors are analyzed for dispersion and frequency-dependent losses. Propagation characteristics of multimode along symmetrical and asymmetrical multiconductor are obtained. Some inherent influences of losses on high-density interconnects and physical dependence of these effects are also discussed.     

Monolayer metallic nanotube interconnects: promising candidates for short local interconnects

Mono- or bi-layer metallic single-wall carbon nanotube interconnects have lateral capacitances more than four times smaller than those of copper interconnects. The resistance and time-of-flight of these monolayer nanotubes would be larger than that of copper interconnects. For short lengths, however, driver resistance is quite dominant, and latency is determined by interconnect capacitance. Monolayer nanotube interconnects are therefore promising candidates for local interconnects. The average capacitance per unit length of these nanotube interconnects can be 50% smaller than that of copper interconnects and that leads to significant saving in power dissipation.