Bias stress effect in low-voltage organic thin-film transistors

The bias stress effect in pentacene organic thin-film transistors has been investigated. The transistors utilize a thin gate dielectric based on an organic self-assembled monolayer and thus can be operated at low voltages. The bias stress-induced threshold voltage shift has been analyzed for different drain-source voltages. By fitting the time-dependent threshold voltage shift to a stretched exponential function, both the maximum (equilibrium) threshold voltage shift and the time constant of the threshold voltage shift were determined for each drain-source voltage. It was found that both the equilibrium threshold voltage shift and the time constant decrease significantly with increasing drain-source voltage. This suggests that when a drain-source voltage is applied to the transistor during gate bias stress, the tilting of the HOMO and LUMO bands along the channel creates a pathway for the fast release of trapped carriers.     

Electrical Characterization of Copper Phthalocyanine Thin-Film Transistors with Fluoride Gate Insulator

Different fluoride materlals are used as gate dielectrics to fabricate copper phthalocyanine （CuPc） thin film transistors （OTFTs）. The fabricated devices exhibit good electrical characteristics and the mobility is found to be dependent on the gate voltage from 10^-3 to 10^-1 cm^2V^-1 s^-1. The observed noticeable electron injection at the drain electrode is of great significance in achieving ambipolar OTFTs, The same method for formation of organic semiconductors and gate dielectric films greatly simplifies the fabrication process. This provides a convenient way to produce high-performance OTFTs on a large scale and should be useful for integration in organic displays.     

Influence of self-assembled monolayer chain length on modified gate dielectric pentacene thin-film transistors

Self-assembled monolayers are widely used to modify the gate dielectric/semiconductor interface in organic thin-film transistors. By modifying the interaction between the molecular semiconductor and the substrate, thin-film ordering and the electronic properties of the semiconducting channel can be controlled. The modified semiconductor/dielectric properties result in macroscopically observed changes in the charge-carrier mobilities, threshold voltages, subthreshold swing and transfer characteristic hysteresis. The latter two are determined by the density of charge-trapping states at the interface. Here, we investigate the influence of the thickness of the self-assembled monolayer, via the alkyl chain length in n-alkyl phosphonic acid-based monolayers on SiO₂, on the electronic properties of pentacene-based organic thin-film transistors. Rather than a monotonic increase or decrease in performance with increasing chain length, we have found that the optimum performance occurs with chains of 8–10 carbon atoms. Atomic force microscopy shows a correlation between pentacene crystalline grain size and transistor performance.     

Enhanced electrical properties of pentacene-based organic thin-film transistors by modifying the gate insulator surface

A reliable surface treatment for the pentacene/gate dielectric interface was developed to enhance the electrical transport properties of organic thin-film transistors (OTFTs). Plasma-polymerized fluorocarbon (CFx) film was deposited onto the SiO₂ gate dielectric prior to pentacene deposition, resulting in a dramatic increase of the field-effect mobility from 0.015 cm²/(V s) to 0.22 cm²/(V s), and a threshold voltage reduction from −14.0 V to −9.9 V. The observed carrier mobility increase by a factor of 10 in the resulting OTFTs is associated with various growth behaviors of polycrystalline pentacene thin films on different substrates, where a pronounced morphological change occurs in the first few molecular layers but the similar morphologies in the upper layers. The accompanying threshold voltage variation suggests that hole accumulation in the conduction channel-induced weak charge transfer between pentacene and CFx.     

Continuous tuning of the threshold voltage of organic thin-film transistors by a chemically reactive interfacial layer

For the design and manufacture of complex integrated circuits, control over the threshold voltage of the transistors is essential. In the present contribution, we present a non-invasive method to tune the threshold voltage of organic thin-film transistors after device assembly over a wide range without any significant degradation of the device characteristics. This is realized by incorporating a thin, chemically reactive siloxane layer bonded to the gate oxide. This results in threshold voltages of around 70 V in the as-prepared devices. By exposing a transistor modified in this way to ammonia at different concentrations, the threshold voltage can be tuned in steps of only a few volts. This treatment affects only the charge density at the semiconductor–dielectric interface, leaving the overall shape of the transistor characteristics and the charge-carrier mobility largely unaltered.     

Performance Improvement of Organic Thin Film Transistors Based on Gate Insulator Polymethyl-Methacrylate-co-Glyciclyl-Methacrylate

Organic thin transistors （OTFTs） on indium tin oxide glass substrates are prepared with polymethyl-methacrylate-co-glyciclyl-methacrylate （PMMA-GMA） as the gate insulator layer and copper phthalocyanine as the organic semiconductor layer. By controlling the thickness, the average roughness of surface is reduced and the OTFT performance is improved with leak current decreasing to 10^-11 A and on/off ratio of 10^4. Under the condition of drain-source voltage -20 V, a threshold voltage of -3.5 V is obtained. The experimental results show that PMMA-GMA is a promising insulator material with a dielectric constant in a range of 3.9-5.0.     

Polymer thin-film transistors with high dielectric constant gate insulators

Field-effect transistors consisting of poly(3-hexylthiophene) have been fabricated with high dielectric constant SrBi₂Ta₂O₉ films working as the gate insulator. Significantly enhanced gate effects were observed in these devices compared to similar transistors with conventional SiO₂ gate dielectric. Our devices exhibited operating voltages around 10 V, as compared to about 100 V for devices employing SiO₂ as the gate dielectric. Moreover, inverters based on such polymer transistors were demonstrated with nice input–output characteristics. PACS 82.35.Cd     

Polymer gate dielectrics with self-assembled monolayers for high-mobility organic thin-film transistors based on copper phthalocyanine

Organic thin-film transistors based on polycrystalline copper phthalocyanine (CuPc) were fabricated by using poly(vinyl alcohol) as gate dielectric. After treatment of the gate dielectric using an octadecyltrichlorosilane self-assembled monolayer, a mobility of up to 0.11 cm²/V s was achieved, which is comparable to that of single-crystal CuPc devices (0.1–1 cm²/V s). The surface morphology was analyzed and the possible reasons for the enhanced mobility are discussed.     

Properties of high-k Ti1−xSixO2 gate dielectric layers prepared at room temperature

High-k Ti_1−xSi_xO₂ gate dielectric layers were prepared at room temperature by RF magnetron sputtering using SiO₂ and TiO₂ targets to investigate their applicability to transparent thin-film transistors as well as metal-oxide-semiconductor field-effect transistors. Based on XRD and XPS analyses, it was found that, regardless of the deposition time, the Ti_1−xSi_xO₂ gate dielectric layers had more stable Si-based phases with stronger Si-O bonds with increasing SiO₂ RF power. As SiO₂ RF power increased, the capacitance of the dielectric layers decreased due to the higher fraction of the Si-based phases, and the leakage current decreased, dominantly because of the decrease in oxygen vacancies due to the formation of stoichiometric SiO₂. The Ti_1−xSi_xO₂ gate dielectric layers exhibited high transparency above 80% and moderate bandgap of 4.1-4.2 eV, which can be applied to transparent thin-film transistors.     

Electrical in‐situ characterisation of interface stabilised organic thin‐film transistors

We report on the electrical in‐situ characterisation of organic thin film transistors under high vacuum conditions. Model devices in a bottom‐gate/bottom‐contact (coplanar) configuration are electrically characterised in‐situ, monolayer by monolayer (ML), while the organic semiconductor (OSC) is evaporated by organic molecular beam epitaxy (OMBE). Thermal SiO₂ with an optional polymer interface stabilisation layer serves as the gate dielectric and pentacene is chosen as the organic semiconductor. The evolution of transistor param‐ eters is studied on a bi‐layer dielectric of a 150 nm of SiO₂ and 20 nm of poly((±)endo,exo‐bicyclo[2.2.1]hept‐5‐ene‐2,3‐dicarboxylic acid, diphenylester) (PNDPE) and compared to the behaviour on a pure SiO₂ dielectric. The thin layer of PNDPE, which is an intrinsically photo‐patternable organic dielectric, shows an excellent stabilisation performance, significantly reducing the calculated interface trap density at the OSC/dielectric interface up to two orders of magnitude, and thus remarkably improving the transistor performance. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

Influence of high energy electron irradiation on the characteristics of polysilicon thin film transistors

The influence of high energy electron (23 MeV) irradiation on the electrical characteristics of p-channel polysilicon thin film transistors (PSTFTs) was studied. The channel 220 nm thick LPCVD (low pressure chemical vapor deposition) deposited polysilicon layer was phosphorus doped by ion implantation. A 45 nm thick, thermally grown, SiO2 layer served as gate dielectric. A self-alignment technology for boron doping of the source and drain regions was used. 200 nm thick polysilicon film was deposited as a gate electrode. The obtained p-channel PSTFTs were irradiated with different high energy electron doses. Leakage currents through the gate oxide and transfer characteristics of the transistors were measured. A software model describing the field enhancement and the non-uniform current distribution at textured polysilicon/oxide interface was developed. In order to assess the irradiation-stimulated changes of gate oxide parameters the gate oxide tunneling conduction and transistor characteristics were studied. At MeV dose of 6×10¹³ el/cm², a negligible degradation of the transistor properties was found. A significant deterioration of the electrical properties of PSTFTs at MeV irradiation dose of 3×10¹⁴ el/cm² was observed.     

A threshold voltage model MOSFETs considering for high-k gate-dielectric fringing-field effect

In this paper, a threshold voltage model for high-k gate-dielectric metal-oxide-semiconductor field-effect transistors （MOSFETs） is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-k gate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-k gate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.     

旋涂速度对制备P3HT有机场效应晶体管性能的影响

采用溶液化的方法制备了以PMMA为绝缘层、P3HT为有源层的有机场效应晶体管.研究了P3HT有源层和PMMA绝缘层的旋涂速度对器件性能的影响.实验结果表明,当P3HT和PMMA的旋涂速度均为2 000 r/min时,器件的性能最佳.峰值场效应迁移率为6.84×10^-2 cm²·V^－1·s^－1.结果表明,选择适当的旋涂速度是一种有效提高溶液化制备有机场效应晶体管性能的方法.     

Surface passivation technology for III-V semiconductor nanoelectronics

The present status and key issues of surface passivation technology for III-V surfaces are discussed in view of applications to emerging novel III-V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors’ group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy (MBE)-grown ultrathin Si layer inserted between III-V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented.     

Improvement of Performance of HfS_2 Transistors Using a Self-Assembled Monolayer as Gate Dielectric

This work details a study based on HfS_(2 )transistors utilizing an n-octadecylphosphonic acid-based self-assembled monolayer(SAM)as the gate dielectric.The fabrication of the SAM-based two-dimensional(2D)material transistor is simple and can be used to improve the quality of the interface of air-sensitive 2D materials.In comparison to HfS_(2) transistors utilizing a conventional Al_2O_(3) gate insulator by atomic layer deposition,HfS_(2) transistors utilizing an SAM as the gate dielectric can reduce the operation region from 4 V to 2 V,enhance the field-effect mobility from 0.03 cm~2/Vs to 0.75 cm~2/Vs,improve the sub-threshold swing from 404 m V/dec to 156 m V/dec,and optimize the hysteresis to 0.03 V,thus demonstrating improved quality of the semiconductor/insulator interface.     

Laser forward transfer of silver electrodes for organic thin-film transistors

Organic thin-film transistors (OTFTs) with top- and bottom-contact configurations were fabricated using silver nano-inks printed by laser forward transfer for the gate and source/drain electrodes with pentacene and poly-4-vinylphenol as the organic semiconductor and dielectric layers, respectively. The volume of the laser-printed Ag pixels was typically in the subpicoliter (0.2–0.4 pl) range. The top-contact OTFTs resulted in lower contact resistance compared to those obtained from the bottom-contact OTFTs, and showed improved overall device performance. The top-contact OTFTs exhibited field-effect mobilities of ∼0.16 cm² V⁻¹ s⁻¹ and on/off current ratios of ∼10⁵.     

Electron-phonon and electron-electron interactions in organic field effect transistors

Recent experiments have demonstrated that the performances of organic FETs strongly depend on the dielectric properties of the gate insulator. In particular, it has been shown that the temperature dependence of the mobility evolves from a metallic-like to an insulating behavior upon increasing the dielectric constant of the gate material. This phenomenon can be explained in terms of the formation of small polarons, due to the polar interaction of the charge carriers with the phonons at the organic/dielectric interface. Building on this model, the possible consequences of the Coulomb repulsion between the carriers at high concentrations are analyzed.     

离子凝胶薄膜栅介石墨烯场效应管

在石墨烯场效应晶体管栅介结构中引入具有良好电容特性或极化特性的材料可改善晶体管性能.本文采用化学气相沉积制备的石墨烯并以PVDF-[EMIM]TF2N离子凝胶薄膜(ion-gel film)作为介质层制备底栅型石墨烯场效应管(graphene-based field effect transistor, GFET),研究其电学特性以及真空环境和温度对GFET性能的影响.结果表明离子凝胶薄膜栅介石墨烯场效应晶体管表现出良好的电学特性,室温空气环境中,与SiO_2栅介GFET相比, ion-gel膜栅介GFET开关比(J_(on)/J_(off))和跨导(g_m)分别提高至6.95和3.68×10~(–2) mS,而狄拉克电压(V_(Dirac))低至1.3 V;真空环境下ion-gel膜栅介GFET狄拉克电压最低可降至0.4 V;随着温度的升高, GFET的跨导最高可提升至6.11×10~(–2) mS.     

Photo-Fries-based photosensitive polymeric interlayers for patterned organic devices

This work reports on the investigation of the photosensitive polymer poly(diphenyl bicyclo[2.2.1]hept-5-ene-2,3-dicarboxylate) (PPNB), which undergoes the photo-Fries rearrangement upon illumination with UV-light, used as interfacial layers in organic electronic devices. Two cases were investigated: the use of a blend of PPNB with poly-vinylcarbazole (PVK) as an interlayer in para-sexiphenyl (PSP) based organic light emitting diodes (OLEDs) and the use of PPNB as gate dielectric layer in organic field effect transistors (OFETs). The photo-Fries rearrangement reaction causes a change of the polymer chemical structure resulting in a change of its physical and chemical properties. The electroluminescence spectra and emission of the PSP OLEDs are not affected when fabricated with a non-UV-illuminated PPNB:PVK blend. However, the electroluminescence is totally quenched in those OLEDs fabricated with UV-illuminated PPNB:PVK blend. Although the dielectric constant of PPNB increases upon UV-treatment, it is demonstrated that those OFETs built with UV-treated PPNB as gate dielectric have lower performance than those OFETs built with non-UV-treated PPNB. Furthermore, the effect of the UV-illumination of PPNB and PPNB:PVK blend on the growth of the small molecules C₆₀ and PSP has been studied by atomic force microscopy. Using photolithography, this kind of photochemistry can be performed to spatially control and tune the optical and electrical performance of organic electronic devices.     

Room-temperature fabrication of ultra-thin ZrOx dielectric for high-performance InTiZnO thin-film transistors

In this letter, indium–titanium–zinc–oxide thin-film transistors with zirconium oxide (ZrO_x) gate dielectric were fabricated at room temperature. In the devices, an ultra-thin ZrO_x layer was formed as the gate dielectric by sol–gel process followed by ultraviolet (UV) irradiation. The devices can be operated under a voltage of 4 V. Enhancement mode operations with a high field-effect mobility of 48.9 cm²/V s, a threshold voltage of 1.4 V, a subthreshold swing of 0.2 V/decade, and an on/off current ratio of 10⁶ were realized. Our results demonstrate that UV-irradiated ZrO_x dielectric is a promising gate dielectric candidate for high-performance oxide devices.