Electrical Characterization of Copper Phthalocyanine Thin-Film Transistors with Fluoride Gate Insulator

Different fluoride materlals are used as gate dielectrics to fabricate copper phthalocyanine （CuPc） thin film transistors （OTFTs）. The fabricated devices exhibit good electrical characteristics and the mobility is found to be dependent on the gate voltage from 10^-3 to 10^-1 cm^2V^-1 s^-1. The observed noticeable electron injection at the drain electrode is of great significance in achieving ambipolar OTFTs, The same method for formation of organic semiconductors and gate dielectric films greatly simplifies the fabrication process. This provides a convenient way to produce high-performance OTFTs on a large scale and should be useful for integration in organic displays.     

Performance Improvement of Organic Thin Film Transistors Based on Gate Insulator Polymethyl-Methacrylate-co-Glyciclyl-Methacrylate

Organic thin transistors （OTFTs） on indium tin oxide glass substrates are prepared with polymethyl-methacrylate-co-glyciclyl-methacrylate （PMMA-GMA） as the gate insulator layer and copper phthalocyanine as the organic semiconductor layer. By controlling the thickness, the average roughness of surface is reduced and the OTFT performance is improved with leak current decreasing to 10^-11 A and on/off ratio of 10^4. Under the condition of drain-source voltage -20 V, a threshold voltage of -3.5 V is obtained. The experimental results show that PMMA-GMA is a promising insulator material with a dielectric constant in a range of 3.9-5.0.     

Fabrication of an Integrated Pixel with an Organic Light-Emitting Diode Driven by Copper Phthalocyanine Organic Thin Film Transistors

An organic integrated pixel with organic light-emitting diodes （OLEDs） driven by organic thin film transistors （OTFTs） is fabricated by a greatly simplified processing. The OTFTs are based on copper phthalocyanine as the active medium and fabricated on indium-tin-oxide （ITO） glass with top-gate structure, thus an organic integrated pixel is easily made by integrating OLED with OTFT. The OTFTs show field-effect mobility of 0.4cm^2/Vs and on/off ratio of 10^3 order. The OLED is driven well and emits the brightness as large as 2100cd/m^2 at a current density of 14.6 μA /cm^2 at -19.7 V gate voltage. This simple device structure is promising in the future large-area flexible OLED displays.     

Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

Carrier mobifity enhancement from 0.09 to 0.59cm2/Vs is achieved for pentacene-based thin-film transistors （TFTs） by modifying the Hf02 gate dielectric with a polystyrene （PS） thin film. The improvement of the transistor＇s performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HI02 surface, the Stranski- Krastanov growth mode on the smooth and nonpolar PS/HfO2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski-Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility.     

Investigation of electrical properties of organic 4-tricyanovinyl-N,N-diethylaniline thin film

Thin films of 4-tricyanovinyl-N,N-diethylaniline (TCVA) with different thickness were prepared using thermal evaporation technique. A relative permittivity, ?_r, of 3.04 was estimated from the dependence of capacitance on film thickness. The current density-voltage (J-V) characteristics of TCVA thin films have been investigated at different temperatures. At low-voltage region, the current conduction in the Au/TCVA/Au sandwich structures obeys Ohm's law. At the higher-voltage regions, the charge transport phenomenon appears to be space-charge-limited current (SCLC) dominated by an exponential distribution of traps with total trap concentration of 1.21 × 10²² m⁻³. In addition, various electrical parameters were determined.     

Low‐voltage,high‐gain,and high‐mobility organic complementary inverters based on N,N′‐ditridecyl‐3,4,9,10‐perylenetetracarboxylic diimide and pentacene

The authors describe an organic complementary inverter with N,N′‐ditridecyl‐3,4,9,10‐perylenetetracarboxylic diimide as an n‐type semiconductor and pentacene as a p‐type semiconductor. Each transistor of the inverter exhibited high carrier mobility: 1.62 cm²/Vs for an n‐type drive transistor and 0.57 cm²/Vs for a p‐type switch transistor. The gain of the inverter reached 125. Another inverter using Ta₂O₅ as a high κ gate dielectric performed well with a gain of 500 and an operation voltage of only 5 V.

     

Effect of modifying a methyl siloxane-based dielectric by a polymer thin film for pentacene thin-film transistors

We report on the fabrication of pentacene thin-film transistors (TFTs) utilizing a spun methyl siloxane-based spin-on-glass (SOG) dielectric and show that these devices can give a similar electrical performance as achieved by using pentacene TFTs with a silicon dioxide (SiO₂) dielectric. To improve the electrical performance of pentacene TFTs with the SOG dielectric, we employed a hybrid dielectric of an SOG/cross-linked poly-4-vinylphenol (PVP) polymer. The PVP film was deposited onto the spun SOG dielectric prior to pentacene evaporation, resulting in an improvement of the saturation field effect mobility (μ_sat) from 0.01 cm²/(V s) to 0.76 cm²/(V s). The good surface morphology and the matching surface energy of the SOG dielectric that was modified with the polymer thin film allow the optimized growth of crystalline pentacene domains whose nuclei are embedded in an amorphous phase.     

Room temperature fabrication Oxide TFT with Y2O3 as a gate oxide and Mo contact

In this investigation, an operating voltage as low as 5 V has been achieved for Oxide TFT with Y₂O₃ as a gate oxide and a-IGZO as an active layer. The OTFT has been fabricated at room temperature using RF sputter. The mobility and threshold voltages are 11.3 cm²/V s and 3.4 V for the device with W/L = 0.8, respectively. The annealing at 400 °C in N₂ containing 5% H₂ ambient has been utilized to improve the electrical performance of TFT. The on-off current which is determined by gate dielectric has been observed to be 10⁴. It has also been observed that the dielectric properties of gate oxide deteriorate on annealing. The dielectric constant of Y₂O₃ is observed in the range between 5.1 and 5.4 measured on various devices.     

Nitrogen Dioxide Sensing Properties and Mechanism of Copper Phthalocyanine Film

Copper phthalocyanine film, a p-type organic semiconductor, is synthesized by vacuum sublimation and its surface morphology is characterized by SEM. A silicon-based copper phthalocyanine film gas sensor for NO2 detection is fabricated by MEMS technology. The results show that the resistance and sensitivity of copper phthalocyanine film decrease obviously as the NO2 concentration increases from Oppm to lOOppm. However, the sensitivity nearly keeps a constant of O. 158 between 30 ppm and 70 ppm. The best working temperature of the gas sensor is 90℃ for NO2 gas concentrations of lOppm, 20ppm and 30ppm, which is much lower than that of general metal oxide gas sensor.     

Low-Voltage Depletion-Mode Indium-Tin-Oxide Thin-Film Transistors Gated by Ba0.4Sr0.6TiO3 Dielectric

We report on the fabrication and characterization of low-voltage indium-tin-oxide （ITO） thin-film transistors （TFTs） gated by a0.4Sr0.6TiO3 （BST） gate dielectric deposited at room temperature. The 400-nm-thick BST film shows a low leakage current density of 6 × 10^-8 A/cm^2 and a high specific capacitance of 83 nF/cm^2 （corresponding εr= 37）. The ITO TFTs gated by such BST dielectric operate in a depletion mode with an operation voltage of 5.0 V. The device exhibits a threshold voltage of -3.7 V, a subthreshold swing of 0.5 V/decade, a field effect mobility of 3.2cm^2/Vs and a current on/off ratio of 1.4× 10^4.     

Near-Infrared Emission from Organic Light-Emitting Diodes Based on Copper Phthalocyanine with a Periodically Arranged Alq3：CuPc/DCM Multilayer Structure

We demonstrate near-infrared organic light-emitting devices with a periodically arranged tris（8-quinolinolato）aluminum （Alq3）：copper phthalocyanine （CuPc）/4-（dicyanomethylene）-2-methyl-6-（4-dimethylaminost-yry）-4H-pyran （DCM） multilayer structure. DCM and Alq3 doped with CuPc were periodically deposited. Room-temperature electrophosphorescence was observed at about 1.1 μm due to transitions from the first excited triplet state to the singlet ground state （T1 - S0） of CuPc. In this device, we utilize the overlap between the Q band πr - π^＊ at about 625nm of the absorption spectra of CuPc and the PL spectra of the DCM. The near-infrared emission intensity of the CuPc-doped Alq3 device with DCM increases about 2.5 times larger than that of the device without DCM. We attribute the efficiency enhancement to the better overlap between the PL spectra of DCM and the absorption spectra of CuPc.     

Amorphous IZO TTFTs with saturation mobilities exceeding 100 cm2/Vs

In this paper we demonstrate the use of amorphous binary In₂O₃–ZnO oxides simultaneously as active channel layer and as source/drain regions in transparent thin film transistor (TTFT), processed at room temperature by rf sputtering. The TTFTs operate in the enhancement mode and their performances are thickness dependent. The best TTFTs exhibit saturation mobilities higher than 10² cm²/Vs, threshold voltages lower than 6 V, gate voltage swing of 0.8 V/dec and an on/off current ratio of 10⁷. This mobility is at least two orders of magnitude higher than that of conventional amorphous silicon TFTs and comparable to or even better than other polycrystalline semiconductors. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Ultra‐high long‐term stability of oxide‐TTFTs under current stress

In this letter the stability of transparent thin‐film transistors (TTFTs) based on the ZnO–SnO₂ (ZTO) material system is investigated. Bottom‐gate devices have been subject to electrical stress via a gate–source bias of 10 V and a drain‐source bias of 10 V leading to a drain–source current of 188 µA. In optimized TTFTs with a composition of [Zn]:[Sn] = 36:64 the relative change of the saturated field effect mobility was less than 1% and the threshold voltage shift was about 320 mV after 1000 hours of operation. This extraordinary stability of ZTO TTFTs underlines their suitability as drivers in active matrix OLED displays. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Performance of Organic Field Effect Transistors with Self-Improved Cu/Organic Interfaces

We fabricate pentacene-based organic field effect transistors （OFETs） with Cu as source and drain （S-D） electrodes. The fabricated devices stored for ten hours under ambient atmospheric conditions exhibit superior performance compared with the as-prepared devices. The field-effect mobility increases from 0. 012 to 0.03 cm^2 V^-1 s^-1, and the threshold voltage downshifts from -14 to -9 V. The on/off current ratios are close to the order of 10^4. The improved performance of the stored devices is attributed to the formation of thin Cu oxide at the Cu electrodes/organic interfaces. These results suggest a simple and available way to optimize device properties and to reduce fabrication cost for OFETs.     

SILC during NBTI Stress in PMOSFETs with Ultra-Thin SiON Gate Dielectrics

Negative bias temperature instability （NBTI） and stress-induced leakage current （SILC） both are more serious due to the aggressive scaling lowering of devices. We investigate the SILC during NBTI stress in PMOSFETs with ultra-thin gate dielectrics. The SILC sensed range from -1 V to 1 V is divided into four parts： the on-state SILC, the near-zero SILC, the off-state SILC sensed at lower positive voltages and the one sensed at higher positive voltages. We develop a model of tunnelling assisted by interface states and oxide bulk traps to explain the four different parts of SILC during NBTI stress.     

Switching Characteristics of Phase Change Memory Cell Integrated with Metal-Oxide Semiconductor Field Effect Transistor

A Ge2Sb2Te5 based phase change memory device cell integrated with metal-oxide semiconductor field effect transistor （MOSFET） is fabricated using standard 0.18 #m complementary metM-oxide semiconductor process technology. It shows steady switching characteristics in the dc current-voltage measurement. The phase changing phenomenon from crystalline state to amorphous state with a voltage pulse altitude of 2.0 V and pulse width of 50ns is also obtained. These results show the feasibility of integrating phase change memory cell with MOSFET.     

Hot-Carrier Stress Effects on GIDL and SILC in 90nm LDD-MOSFET with Ultra-Thin Gate Oxide

Hot-carrier degradation for 90 nm gate length lightly-doped drain （LDD） NMOSFET with ultra-thin （1.4 nm） gate oxide is investigated under the low gate voltage stress （LGVS） and peak substrate current （Isub max） stress. It is found that the degradation of device parameters exhibits saturating time dependence under the two stresses. We concentrate on the effect of these two stresses on gate-induced-drain leakage （GIDL） current and stress induced leakage current （SILC）. The characteristics of the GIDL current are used to analyse the damage generated in the gate-to-LDD region during the two stresses. However, the damage generated during the LGVS shows different characteristics from that during Isub stress. SILC is also investigated under the two stresses. It is found experimentally that there is a linear correlation between the degradation of SILC and that of threshold voltage during the two stresses. It is concluded that the mechanism of SILC is due to the combined effect of oxide charge trapping and interface traps for the ultra-short gate length and ultra-thin gate oxide LDD NMOSFETs under the two stresses.     

Degradation of Ultra-Thin Gate Oxide NMOSFETs under CVDT and SHE Stresses

Degradation of device under substrate hot-electron (SHE) and constant voltage direct-tunnelling (CVDT)stresses are studied using NMOSFET with 1.4- nm gate oxides. The degradation of device parameters and the degradation of the stress induced leakage current (SILC) under these two stresses are reported. The emphasis of this paper is on SILC and breakdown of ultra-thin-gate-oxide under these two stresses. SILC increases with stress time and several soft breakdown events occur during direct-tunnelling (DT) stress. During SHE stress, SILC firstly decreases with stress time and suddenly jumps to a high level, and no soft breakdown event is observed. For DT injection, the positive hole trapped in the oxide and hole direct-tunnelling play important roles in the breakdown. For SHE injection, it is because injected hot electrons accelerate the formation of defects and these defects formed by hot electrons induce breakdown.     

Modeling of a Silicon Nanowire pH Sensor with Nanoscale Side Gate Voltage

A silicon nanowire （Si-NW） sensor for pH detection is presented. The conductance of the device is analytically obtained, demonstrating that the conductance increases with decreasing oxide thickness. To calculate the electrical conductance of the sensor, the diffusion-drift model and nonlinear Poisson-Boltzmann equation are applied. To improve the conductance and sensitivity, a Si-NW sensor with nanoscaie side gate voltage is offered and its characteristics are theoretically achieved. It is revealed that the conductance and sensor sensitivity can be enhanced by adding appropriate side gate voltages. This effect is compared to a similar fabricated structure in the literature, which has a wire with a rectangular cross section. Finally, the effect of NW length on sensor performance is investigated and an inverse relation between sensor sensitivity and NW length is achieved.     

A Physics-Based Compact Direct-Current and Alternating-Current Model for AlGaN/GaN High Electron Mobility Transistors

A set of analytical models for the dc and small signal characteristics of AIGaN/GaN high electron mobility transis- tors （HEMTs） are presented. A modified transferred-electron mobility model is adapted and a phenomenological low-field mobility model is developed. We calculate the channel charge considering the neutralization of donors and the contribution of free electrons in the AlGaN layer. The gate-to-source and gate-to-drain capacitances are obtained analytically, and the cut-off frequency is predicted. The models are implemented into the HSPICE simulator for the dc, ac and transient simulations and verified by experimental data for the first time. A high efficiency class-E GaN HEMT power amplifier is designed and simulated by the HSPICE to verify the applicability of our models.