一种新型的晶体管级改进Booth编码单元电路

文章提出了一种新的高速低功耗晶体管级改革Booth编码单元电路。该电路组合了CMOS逻辑电路和传递管逻辑电路，采用高速低耗XOR和XNOR电路，仅用了30个晶体管就实现了改进Booth编码。在0.35μm的工艺条件下，HSPICE的仿真结果表明，电源电压3.3V和频率100MHz条件下，该改进Booth编码电路的延迟为0.34ns，平均功耗为0.13mW。     

Custom Network Design and Pricing Tools

Selling national and international data networking solutions (WAN and LAN) is an essential part of the BT solutions business. In this highly competitive sector the technology is evolving fast and consequently there are frequent enhancements of the product and service offerings. With this goes a tendency to increase the complexity of the pricing and discount schemes as competitors jostle to differentiate their products in the market-place.The BT data network sales organisation has to keep up with all these market changes. To assist with this, BT has invested heavily in a range of bespoke sales tools to support mass customisation of this range of solutions, in order to help improve their turnover, market reach and win rate. One of these tools is an application called SPEED (system pricing and end-to-end design) which is used at the consultative selling and design stages. SPEED is installed on the portable computers used by the account management teams. It aims to incorporate the 'mind of the expert designer'—best practice design principles and a compendium of the latest product and service offerings with up-to-date tariff and discount structures. It enables customers' requirements to be modelled and priced both accurately and quickly.SPEED provides a considerable advantage to the sales force in terms of reduced sales cycle, flexibility and accuracy of response to the customer. It also eliminates errors and omissions in the design and order-entry processes.This paper will focus on how SPEED delivers real business value to the customer and to BT.     

UHF RFID阅读器基带处理接收端电路的设计

根据UHF RFID阅读器实现的IQ两路正交调制解调的零中频方案,设计和实现了阅读器基带处理芯片接收端电路,包括电路总体结构及解调器、解码器等关键模块的设计,完成其RTL设计、仿真及FPGA原型验证.该设计在物理层数据编码、调制方式及其他关键技术进行了改进,性能上有很大的提高.     

Domain Specific Tools and Methods for Application in Security Processor Design

Security processors are used to implement cryptographic algorithmswith high throughput and/or low energy consumption constraints. The designof these processors is a balancing act between flexibility and energy consumption.The target is to create a processor with just enough programmability to covera set of algorithms—an application domain. This paper proposes GEZEL,a design environment consisting of a design language and an implementationmethodology that can be used for such domain specific processors. We use thesecurity domain as driver, and discuss the impact of the domain on the targetarchitecture. We also present a methodology to create, refine and verify asecurity processor.     

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

The Cell Broadband Engine (Cell BE) is a multicore system-on-chip (SoC), implemented in a 90-nm high-performance silicon-on-insulator (SOI) technology, and optimized, within the triple constraints of area, power, and performance, to run at frequencies in excess of 3 GHz. The large scale of the design ($sim$75 million logic transistors, and about 750 000 latches and flip-flops), high-volume requirements, and the desire to support multiple manufacturing facilities dictated a need for very robust circuit practices, but at the same time, the high-frequency goal drove the use of more aggressive styles in certain critical regions of the design. This paper describes the local clock design, along with the various latches and flip-flops deployed, followed by a discussion of the circuit techniques used for the digital logic implementation, including special considerations for high-speed synthesized control logic, semi-custom and full-custom static circuit design and full-custom dynamic logic circuits. In addition, the synergistic processor element (SPE) circuit design is described, followed by the techniques and issues associated with the SRAM design. Finally, the methods used for electrical verification are described, these being an important part of the strategy for ensuring overall design robustness and first-silicon success.     

模拟接口电路与数字信号处理器的接口设计

介绍模拟接口电路TLC320AD50C与数字信号处理器TMS320VC5402的接口设计。     

A 32-Bit Custom VLSI Processor for Communications Network Nodes

Aimed at the application to processors used in communications networks, three kinds of custom CMOS VLSI chips, each integrating approximately 10 kilogates, were developed. During the development of these chips, we overcame various restrictions on the VLSI design, such as input/output pin limitations, bug correction difficulty, and input/output signal delay. A combination of the software and hardware simulators efficiently eliminated logic errors. Microprogram control memory is placed externally to VLSI chips to facilitate tentative correction of possible remaining errors. Two types of processors sharing uniform architecture were also developed for an overall optimum cost-effectiveness using these VLSI chips. One uses all three kinds of VLSI chips and is suitable for switching and communications processing applications. The other includes one VLSI chip and consists of a single printed circuit board. It is suitable for a portable console processor or a processor imbedded in various equipment. These VLSI processors are being introduced in large numbers in communications networks in Japan.     

基于雷达极化的数字信号处理机电路设计

结合双极化电磁波雷达接收机原理,系统地讨论了组成数字信号处理机的核心——DSP芯片、程序存储器、A/D转换器和双端口RAM等元器件的选择以及相应电路设计问题。给出了详实的应用电路,并对电路的工作原理进行了阐述。     

On the Design of a High-Performance LSI Circuit Digital Signal Processor for Communication

This paper describes the design of a highly efficient CMOS LSI circuit digital signal processor (FDSP3). To realize an operating cycle rate of 10 MHz and a throughput rate of 0.6 μs per second-order filter section, considerable care has been paid to the design of software structures and hardware circuitry. Basic program routines and some application examples are also shown. These examples illustrate the high efficiency of the developed DSP device.     

TMS320DM642为核心的视频图像处理器外围电路设计

探讨以TMS320DM642为核心的实时视频数字图像处理器的总体结构。重点阐述图像处理器的外围电路设计,包括其各部分功能以及所选用的主要器件,同时针对视频图像处理算法的性质,对视频图像处理过程中图像数据的存放位置给出了一定原则。该设计系统充分发挥数字信号处理器(DSP)TMS320DM642的高性能特点。最后指出该设计系统的主要特点及其自身具有的优越性。     

双里德-索罗门码信号处理器的交织、反交织理论及电路设计

利用微和硬件结合的方法，设计了新颖的里德－索罗门信号处理器交织，反交织电路。实验证明当磁迹丢失数据达４０％时，仍能利用插恢复数据。该电路具有可集，电路简捷及可进行实时交织，反交织运算等优点。     

A Full Custom Integrated Circuit for Document Analysis Systems

This paper describes the architecture and design methodology used to produce a new custom IC intended for automatic document analysis. The circuit implements the entire operative part of a dedicated microprogrammed processor for the next generation of page readers which include items such as Optical Character Recognition (OCR) and different codings for graphics and images. The chip provides a wide range of powerful functions, performing up to three operations per cycle. It includes about 10 000 transistor sites and occupies an area of 20 mm/sup 2/. A standard 6-/spl mu/m NMOS technology was used. Typical clock frequency is 2 MHz. The layout was obtained using a highly regular architecture and some automatically generated structures. New CAD tools provided an efficient and short design procedure.     

高端虚拟演播室系统设计

虚拟演播室系统是传统演播室的色键技术与计算机图形图像处理技术相结合的产物。它将计算机制作的虚拟场景与电视摄像机现场拍摄的人物进行数字化合成从而获得完美的合成电视画面。本文在分析虚拟演播室系统工作原理的基础上,着重介绍了系统构成及设计问题,并给出了设计举例。     

IBM PC／XT外逸电子计数接口电路的设计与实现

外逸电子数目准确检测是智能型外逸电子传感器的关键所在。本文介绍一种ＩＢＭＰＣ／ＸＴ外逸电子计数接口电路的原理和设计方法，并给出了在中断方式下进行数据处理的硬件和软件框图。     

EDA在“模拟集成电路设计”教学中的应用

针对本校大部分高年级学生轻基础重实践的特点,笔者在"模拟集成电路设计"课程的教学过程中,尝试着将(EDA软件)和课程内容合理结合,进行实践教学。文中给出了一个体现该教学思想的教学实例,教学结果表明学生的学习热情较高,大部分学生能在实践教学过程中掌握相关理论,有较好的动手能力。     

嵌入式处理器的TLB电路设计

为了提高基于虚拟存储技术的嵌入式处理器的性能,本文提出了一种用于高效加速地址转换的TLB电路结构。该电路采用64-entries的全关联结构,硬件支持基于段及不同大小页的转换方式。通过VCS和Nanosim联合仿真对电路结构和性能进行了验证,仿真结果表明,系统中加入TLB电路以后性能有显著的提高。     

FPGA硬核处理器系统加速数字电路功能验证的方法

为了缩短专用集成电路和片上系统的功能验证周期,该文提出FPGA硬核处理器系统加速数字电路功能验证的方法。所提方法综合软件仿真功能验证和现场可编程门阵列原型验证的优点,利用集成在片上系统现场可编程门阵列器件中的硬核处理器系统作为验证激励发生单元和功能验证覆盖率分析单元,解决了验证速度和灵活性不能统一的问题。与软件仿真验证相比,所提方法可以有效缩短数字电路的功能验证时间;在功能验证效率和验证知识产权可重用方面表现优于现有的FPGA原型验证技术。     

Circuit Placement, Chip Optimization, and Wire Routing for IBM IC Technology

Recent advances in integrated circuit technology have imposed new requirements on the chip physical design process. At the same time that performance requirements are increasing, the effects of wiring on delay are becoming more significant. Larger chips are also increasing the chip wiring demand, and the ability to efficiently process these large chips in reasonable time and space requires new capabilities from the physical design tools. Circuit placement is done using algorithms which have been used within IBM for many years, with enhancements as required to support additional technologies and larger data volumes. To meet timing requirements, placement may be run iteratively using successively refined timing-derived constraints. Chip optimization tools are used to physically optimize the clock trees and scan connections, both to improve clock skew and to improve wirability. These tools interchange sinks of equivalent nets, move and create parallel copies of clock buffers, add load circuits to balance clock net loads, and generate balanced clock tree routes. Routing is done using a grid-based, technology-independent router that has been used over the years to wire chips. There are numerous user controls for specifying router behavior in particular areas and on particular interconnection levels, as well as adjacency restrictions.     

S698M SoC芯片中EDAC模块的设计与实现

EDAC检错纠错模块在电子、通信以及航空航天等领域有着广泛的应用。本文主要介绍了利用[39，32]扩展海明码的EDAC模块的基本原理和用VHDL语言设计实现EDAC的设计实现，该模块在XILINXISE软件开发环境下通过设计、综合、仿真，验证了设计的正确性。     

嵌入式处理器中写缓冲电路的设计

为了减少CPU对主存进行写操作时的等待时间,提高嵌入式系统的整体效率,设计了一款含有8个数据缓冲槽和4个地址缓冲槽的写缓冲。该写缓冲采用特殊的移位控制电路和附加的标志位,实现数据、地址的自动移位和映射功能。利用HSIM仿真工具对电路进行了仿真和验证,结果表明,该写缓冲能正确快速地实现数据与地址的先进先出(FIFO)功能,有效地减少了CPU的等待时间,提高了系统的整体效率。