Bandwidth Extension Techniques for CMOS Amplifiers

Inductive-peaking-based bandwidth extension techniques for CMOS amplifiers in wireless and wireline applications are presented. To overcome the conventional limits on bandwidth extension ratios, these techniques augment inductive peaking using capacitive splitting and magnetic coupling. It is shown that a critical design constraint for optimum bandwidth extension is the ratio of the drain capacitance of the driver transistor to the load capacitance. This, in turn, recommends the use of different techniques for different capacitance ratios. Prototype wideband amplifiers in 0.18-mum CMOS are presented that achieve a measured bandwidth extension ratio up to 4.1 and simultaneously maintain high gain (>12 dB) in a single stage. Even higher enhancement ratios are shown through the introduction of a modified series-peaking technique combined with staggering techniques. Ultra-wideband low-noise amplifiers in 0.18-mum CMOS are presented that exhibit bandwidth extension ratios up to 4.9     

Low-Complexity Ultra-Wide-Band Communications

Low-complexity low-power ultra-wide-band (UWB) radios are required for low data rate (LDR, < 100 kbps) short- range applications. Potential low-power air interface candidates are impulse radio UWB and FM-UWB. The use of simple (noncoherent) radio architectures, a low supply voltage and duty cycling pave the way to low power consumption. Interference mitigation is an important requirement for today's UWB receivers. Processing gain and filtering may be applied in the physical layer, whereas detect and avoid strategies work at MAC level. Constant-envelope FM-UWB uses high modulation index analog FM for spreading. Instantaneous despreading in the receiver, combined with processing gain make this system an interesting option for robust LDR personal area network systems.     

Power-Combining Transformer Techniques for Fully-Integrated CMOS Power Amplifiers

Fully integrated CMOS power amplifiers (PAs) with parallel power-combining transformer are presented. For the high power CMOS PA design, two types of transformers, series-combining and parallel-combining, are fully analyzed and compared in detail to show the parasitic resistance and the turn ratio as the limiting factor of power combining. Based on the analysis, two kinds of parallel-combining transformers, a two-primary with a 1:2 turn ratio and a three-primary with a 1:2 turn ratio, are incorporated into the design of fully-integrated CMOS PAs in a standard 0.18-mum CMOS process. The PA with a two-primary transformer delivers 31.2 dBm of output power with 41% of power-added efficiency (PAE), and the PA with a three-primary transformer achieves 32 dBm of output power with 30% of PAE at 1.8 GHz with a 3.3-V power supply.     

Broad-Band Design Techniques for Transimpedance Amplifiers

In this paper, a novel bandwidth enhancement technique based on the combination of capacitive degeneration, broad-band matching network, and the regulated cascode (RGC) input stage is proposed and analyzed, which turns the transimpedance amplifier (TIA) design into a fifth-order low-pass filter with Butterworth response. This broad-band design methodology for TIAs is presented with an example implemented in CHRT 0.18-mum 1.8-V RF CMOS technology. Measurement data shows a -3-dB bandwidth of about 8 GHz with 0.25-pF photodiode capacitance. Comparing with the core RGC TIA without capacitive degeneration and broad-band matching network, this design achieves an overall bandwidth enhancement ratio of 3.6 with very small gain ripple. The transimpedance gain is 53 dBOmega with a group delay of 80plusmn20 ps. The chip consumes only 13.5-mW dc power and the measured average input-referred noise current spectral density is 18 pA/radicHz up to 10 GHz     

A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

To employ the distributed amplification technique for the design of ultra-wide-band low-noise amplifiers, the poor noise performance of the conventional distributed amplifiers (DAs) needs to be improved. In this work, the terminating resistor of the gate transmission line, a main contributor to the overall DA's noise figure, is replaced with a resistive-inductive network. The proposed terminating network creates an intentional mismatch to reduce the noise contribution of the terminating network. The degraded input matching at low frequencies can be tolerated for ultra-wide-band applications as they need to operate above 3 GHz. Implemented in a 0.13 mum CMOS process, the proposed DA achieves a flat gain of 12 dB with an average noise figure of 3.3 dB over the 3- to 9.4-GHz band, the best reported noise performance for a CMOS DA in the literature. The amplifier dissipates 30 mW from two 0.6-V and 1-V dc power supplies.     

宽带、超宽带光纤放大器研究进展

目前,实现宽带、超宽带光纤放大器的技术主要有四种:宽带掺铒光纤放大(EDFA)技术、宽带拉曼放大技术、宽带混合放大技术和光纤参量放大技术.综述了宽带和超宽带光纤放大器的研究现状,并分别分析了其特点及发展趋势.     

应用于多标准无线通信的宽带Doherty功率放大器

提出一种新型输出合路器结构,以增强两路对称Doherty功率放大器(DPA)带宽性能。通过在峰值放大器输出端插入一段四分之一波长传输线,以补偿低功率区域中的载波放大器负载阻抗的稳定性。为此,峰值放大器输出匹配网络被用于在其关闭时将辅放大器的输出阻抗转换成准短路,并且当其开启时实现适当的阻抗匹配。且峰值放大器输出端插入一段四分之一波长传输线后取消了辅放大器输出端的补偿线,极大地拓宽DPA的带宽。最后,采用GaN晶体管CGH40010F基于新型合路器结构设计一款宽带Doherty功率放大器样品并进行实物加工测试。测试结果显示,新型宽带Doherty功率放大器实物在1.45~2.45GHz的1GHz带宽内,饱和输出功率为43.81~45.43dBm,饱和效率在53%~63%之间,输出功率回退6dB处的效率在40%以上,相对带宽高达51%。并采用WCDMA调制信号对功放电路的线性度进行了测试,结果表明电路的线性度良好。     

Design Considerations for 60 GHz Transformer-Coupled CMOS Power Amplifiers

This work discusses the design methodologies for efficient power generation at mm-wave frequencies in CMOS. Passive elements play an important role in PA design, as they determine both the output power and power gain of the circuit. In this work, we have developed a methodology for design of transformer-coupled power amplifiers. A distributed model of on-chip transformers has been developed that can predict the performance up to very high frequencies, is length scalable and uses only a few parameters , compared to a complete lumped model. Using the model, a two-stage transformer-coupled PA has been designed in 90 nm CMOS. The prototype has one of the highest output powers reported for a 60 GHz CMOS PA. A three-stage improved design with higher gain and efficiency is reported, stressing the importance of driver stage design at these frequencies. The PA has been integrated into a complete transmitter and tested with 10 Gb/s QPSK modulated data.     

低压低功耗CMOS电流反馈运算放大器设计

利用电流传输器CCII+作为输入(输出)缓冲器,使用0.18μMCMoS工艺设计了低压低功耗电流反馈运算放大器,模拟结果初步获得了与增益无关的23.3MHz带宽及27.7V/μS的转换速率.     

Design Procedure for Two-Stage CMOS Transconductance Operational Amplifiers: A Tutorial

This paper deals with well-defined designcriteria for two-stage CMOS transconductance operational amplifiers. A novel and simple designprocedure is presented, which allows electricalparameters to be univocally related to the value ofeach circuit element and biasing value. Unlikeprevious methods, the proposed one is suited for apencil-and-paper design and yields accurateperformance optimization without introducingunnecessary circuit constraints. Bandwidthoptimization strategies are also discussed. SPICE simulations based on the proposed procedures aregiven which closely agree the expected results.     

Desensitized CMOS Low-Noise Amplifiers

The minimum attainable noise figure for scaled- CMOS low-noise amplifiers (LNAs) is limited by impedance mismatches such as the well-known noise/power tradeoff. In this paper, we show that a power-constrained optimization of the device noise resistance parameter, R_n, significantly reduces the impact of mismatches and variations and leads to an almost simultaneous noise and power match. This process, called desensitization, makes the design largely immune to measurement and modeling errors and manufacturing variations, and significantly reduces frequency-dependent noise mismatches in wide-band LNAs. Measured data from devices and desensitized LNAs designed on 180-nm and 90-nm CMOS processes shows that: (1) a device size selected for optimum R_nmiddot is less sensitive to source impedance mismatches and provides a wide-band noise match; and (2) LNAs approach a simultaneous input and noise match, and exhibit significant improvements (ges 2x) in their wide-band noise performance.     

CMOS分数频率综合器设计技术

现代无线通信要求频率综合器同时满足快速切换时间，小信道宽度和低噪声性能三方面的要求。分数N频率综合器在这方面的优良特性使得它在现代无线通信系统中被广泛使用。文章系统地讨论了用CMOS工艺实现分数频率综合器的技术问题，并对频率综合器的发展方向和面临的挑战提出了一些看法。     

Power-Aware Multiband–Multistandard CMOS Receiver System-Level Budgeting

A systematic system-level design methodology for multiband-multistandard (MB-MS) wideband/reconfigurable CMOS receivers is presented. The methodology determines the specifications (noise figure (NF) and linearity) for each building block to minimize the overall power consumption. System-level simulations show that the gain variation of the LNA for various bands/standards is an important factor in minimizing the power consumption for any MB-MS receiver. Analytical expressions for the optimum gain variation of the LNA, NF, and input-referred third-order intercept point of each building block are presented. The design methodology is applied to a wideband receiver covering Global Systems for Mobile Communications (GSM) 900- and 1900-MHz bands, Global Positioning Systems (GPS), and wideband code-division multiple-access (WCDMA) standards. As an example, the estimated power consumption is reduced by 40% when compared with the approach where the gain of the LNA is constant.     

Performance Analysis and Design of Triple-Resonance Interstage Peaking for Wide-Band Cascaded CMOS Amplifiers

The analysis and design of the two promising candidates for interstage bandwidth enhancement of integrated wide-band cascaded amplifiers (CAs), namely series-shunt (SH) and shunt-series (HS) triple-resonance peaking, are presented. The principal operation of both peaking networks is described qualitatively in time-domain where the inherent bandwidth superiority of SH peaking is revealed. With the help of triple resonance concept, a rigorous and insightful analysis is then given in frequency domain. Analytical equations applicable to both networks have been derived to enable the proper inductance selection and to quantify the bandwidth advantage of SH peaking. In addition, various frequency characteristics of the networks are discussed through the investigation of their triple resonant frequency locations. This is followed by detailed analysis on the important nonidealities due to transistors gate resistance and inductors' losses. The effectiveness of theoretical analysis is demonstrated via design and simulation of SHCA and HSCA with identical number of stages, gain and power consumption. The results show good agreement between theoretical analysis and simulation where the SHCA outperforms its HS counterpart in bandwidth while other performances are practically identical.     

Current-Mode High-Accuracy High-Precision CMOS Amplifiers

In low-voltage, deep sub- mum analog CMOS circuits, the accuracy and precision can be limited by the finite gain as well as by the input offset and 1/f noise voltages of opamps. Here, we show how to design high-accuracy high-precision CMOS amplifiers by properly applying dynamic element matching to a second-generation current conveyor (CCII); if all of the critical, nominally identical transistor pairs are dynamically matched, the resulting amplifier has low residual input offset and noise voltages. When compared with chopper or traditional dynamic element-matching amplifiers, the proposed approach alleviates the tradeoff between output swing and output resistance and is more robust against the finite opamp gain. Transistor-level simulations confirm theoretical results.     

CMOS Power-Efficient Buffers and Amplifiers

In this paper, some topologies of novel power-efficient single-ended and fully differential amplifiers and buffers are presented. The reduction of the power dissipation has been ensured through the application of an adaptive biasing architecture which gives a current dependent on the input differential voltage. This allows the minimization of the stand-by power consumption without affecting the transient characteristics. The proposed topology, implemented in a standard CMOS technology, has been applied in the design of input and output stages of low-power amplifiers and voltage buffers, considering them also in the fully differential version. Simulation and measurement results showing good general performance will be also presented.     

Low-Power High-Drive CMOS Operational Amplifiers

Low-power CMOS op amps with high-drive capability and good settling characteristics are described. One circuit, occupying 150 mils/sup 2/ of active area and consuming 1 mW of power drives a capacitive load of up to 150 pF with greater than +-2.5 V/µs slew rates and less than 3.5 µs settling time to 0.1 percent. A somewhat larger circuit drives low-resistance (e.g., 600 Omega) and high-capacitance (1000 pF) loads with better slew rates and settling time. These circuits are suitable for applications in such systems as charge-redistribution codecs and switched-capacitor filters.     

CMOS电路混合整数最优化及设计方法

本文给出了一类CMOS门电路的最优设计问题,并给出了在一定约束条件下最大倒相链级数优化的混合整数优化模型。根据一种连续整数规划求解方法,本文提出了对CMOS电路混合整数优化的设计方法和步骤。最后,本文给出了一个实际的设计结果。     

CMOS集成电路的功耗优化和低功耗设计技术

总结了当前已发展出的各个层次的CMOS低功耗设计技术和低功耗设计方法学的研究进展.重点介绍了时序电路的优化、异步设计、高层次电路设计和优化技术.     

基于提高效率方法的CMOS功率放大器设计

利用共源共栅电感可以提高共源共栅结构功率放大器的效率。这里描述了一种采用共源共栅电感提高效率的5.25GHz WLAN的功率放大器的设计方法,使用CMOS工艺设计了两级全差分放大电路,在此基础上设计输入输出匹配网络,然后使用ADS软件进行整体仿真,结果表明在1.8V电源电压下,电路改进后于改进前相比较,用来表示功率放大器效率的功率附加效率（PAE）提高了两个百分比。最后给出了功放版图。