Power bus isolation using power islands in printed circuit boards

Power islands are often employed in printed circuit board (PCB) designs to alleviate the problem of power bus noise coupling between circuits. Good isolation can be obtained over a wide frequency band due to the large series impedance provided by the gap between the power islands. However, power bus resonances may degrade the isolation at high frequencies. The amount of isolation also depends on the type of connection between power islands and the components on the board. This paper experimentally investigates the effectiveness of several power island structures up to 3.0 GHz     

Power bus decoupling on multilayer printed circuit boards

Guidelines for the selection and placement of decoupling capacitors that work well for one-sided or two-sided printed circuit boards are not appropriate for multilayer boards with power and ground planes. Boards without internal planes take advantage of the power bus inductance to help decouple components at the higher frequencies. An effective decoupling strategy for multilayer boards must account for the low inductance and relatively high capacitance of the power bus     

Power-bus decoupling with embedded capacitance in printed circuit board design

This paper experimentally investigates the effectiveness of embedded capacitance for reducing power-bus noise in high-speed printed circuit board designs. Boards with embedded capacitance employ closely spaced power-return plane pairs separated by a thin layer of dielectric material. In this paper, test boards with four embedded capacitance materials are evaluated. Power-bus input impedance measurements and power-bus noise measurements are presented for boards with various dimensions and layer stack ups. Unlike discrete decoupling capacitors, whose effective frequency range is generally limited to a few hundred megahertz due to interconnect inductance, embedded capacitance was found to efficiently reduce power-bus noise over the entire frequency range evaluated (up to 5 GHz).     

Circuit models for power bus structures on printed circuit boards using a hybrid FEM-SPICE method

Power bus structures consisting of two parallel conducting planes are widely used on high-speed printed circuit boards. In this paper, a full-wave finite-element method (FEM) method is used to analyze power bus structures, and the resulting matrix equations are converted to equivalent circuits that can be analyzed using SPICE programs. Using this method of combining FEM and SPICE, power bus structures of arbitrary shape can be modeled efficiently both in the time-domain and frequency-domain, along with the circuit components connected to the bus. Dielectric loss and losses due to the finite resistance of the power planes can also be modeled. Practical examples are presented to validate this method.     

Estimating the noise mitigation effect of local decoupling in printed circuit boards

Local decoupling, i.e., placing decoupling capacitors sufficiently close to device power/ground pins in order to decrease the impedance of power bus at frequencies higher than the series resonant frequency, has been studied using a modeling approach, a hybrid lumped/distributed circuit model established and an expression to quantify the benefits of power bits noise mitigation due to local decoupling developed. In this work, a test board with a local decoupling capacitor was studied and the noise mitigation effect due to the capacitor placed adjacent to an input test port was measured. Closed-form expressions for self and mutual inductances of vias are developed, so that the noise mitigation effect can then be estimated using the previously developed expression. The difference between the estimates and measurements is approximately 1 dB, which demonstrates the application of these closed-form expressions in the PCB power bus designs. Shared-via decoupling, capacitors sharing vias with device power/ground pins, is also modeled as an extreme case of local decoupling.     

Investigation of environmental reliability of optical polymer waveguides embedded on printed circuit boards

In this paper, the effects of environmental stresses on the properties of polymeric optical waveguides were investigated. Optical multimode waveguides were embedded on printed circuit boards by employing commercial polymers. Three optical-PCB constructions varying in board structure and in optical build-up materials were compared. The guide systems were subjected to four different tests: damp heat-high humidity, isothermal annealing, thermal shock and environmental flowing multigas test. Isothermal annealing reduced the refractive index to greatest extent. The optical-PCB structure with optical surface build-up layer was observed to be more vulnerable under temperature shock when compared with the O-PCB with optical inner layer. The buffer layer beneath the optical build-up was found to improve the stability of the optical waveguides significantly. The results indicated of a wavelength dependence to the aging factor with a failure mechanism. The factors affecting the performance and reliability of polymer-based optical waveguides on PCBs were discussed.     

The effect of test system impedance on measurements of groundbounce in printed circuit boards

Based on the 3D-FDTD approach, an efficient equivalent model employing the embedded resistive voltage source is proposed to simulate the effect of test system impedance on the measurement of the ground bounce noise for the power planes structure in the printed circuit boards (PCB). Compared with the measured results by vector network analyzer, this equivalent model well predicts the impedance behavior of the V_cc/GND power planes. The influences of different probe loading conditions of the test system on the measurement of impedance behavior are studied. It is found that the effects of the probing loads on the measurement of the ground bounce noise is significant at the frequencies near the dc point and resonance, but the influences of the probes are small at the frequencies far from resonance. In addition, the transfer characteristics of the power bus in the realistic digital circuits with decoupling capacitance being considered are simulated in the FDTD model. The difference of the transfer behavior between the realistic case without coaxial feed and the measured results with probing effects is also numerically compared. We find that the ground bounce noise in the real circuit can be accurately measured at most frequencies, where the power planes act in very low impedance, except at the frequencies near dc and resonance frequencies, where the power planes behave in relatively higher impedance characteristics     

A simple and effective model for electromagnetic bandgap structures embedded in printed circuit boards

Using a transmission-line model and considering a simple lumped-element substitute for the patch-via structure, a first-order, but detailed, quantitative and qualitative analysis of the filtering properties of a metallo-dielectric electromagnetic bandgap structure embedded in a printed circuit board is presented. This model is able to describe the resonant properties of the structure as well as its pass-band and stop-band regions.     

An accurate experimental method for characterizing transmission lines embedded in multilayer printed circuit boards

We have developed an accurate method for measuring the complex propagation constant and characteristic impedance of transmission lines embedded in multilayer printed circuit boards. It is based on mathematical error-removal schemes using two different length transmission lines and an advanced via-hole structure that minimizes coupling. Consequently, associated errors, due to discontinuities and interference can be effectively eliminated, and the frequency dependencies of the transmission line parameters can be clarified in wide frequency bandwidths. We verified the validity of this method in frequency ranges up to at least 18 GHz, by comparing the determined values with the theory derived from transverse electromagnetic (TEM) approximations.     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

A hierarchical analog test bus framework for testing mixed-signal integrated circuits and printed circuit boards

Progress in analog circuit testing has been hindered by the lack of structured design-for-testability methodologies. With the increasing complexity of analog/mixed-signal circuits, test program development time is now a major obstacle in achieving shorttime-to-market, while production testing cost is a prominent factor in total production cost. TheAnalog Autonomous Test is a structured design-for-testability scheme for analog circuits. Originally developed for testing analog circuits at chip level, AAT extends naturally to cover testing of mixedsignal integrated circuits mounted on printed circuit boards. With the addition of an analog test bus to PCBs, testability for analog components (bothcore circuits andglue circuits) can be improved, in a manner similar to that achieved for digital boards by the IEEE 1149.1 boundary scan scheme. Details on the implementation of thisAnalog Autonomous Test Bus, both at chip level and board level, are presented here. Its limitations and potential applications are also discussed.     

MT-compatible laser-ablated interconnections for optical printed circuit boards

Integration of optical interconnections on a printed circuit board (PCB) is very challenging, since compatibility should be maintained with standard PCB manufacturing technology. This paper describes the use of laser ablation, a technique already used in PCB manufacturing for drilling microvias, as a suitable technique for the fabrication of multimode polymer waveguides, micromirrors, alignment features, and microlenses. A frequency-tripled Nd-YAG laser and a KrF excimer laser are used, both mounted on the same stage, resulting in very high alignment accuracies. This paper demonstrates a parallel optical link over approximately 5-cm-long PCB integrated waveguides, fully connected using a standard MT-based connector. This proves that laser ablation can be a key technology in optical board manufacturing to reach the stringent coupling tolerances.     

废旧印制电路板资源化处理现状

在大力倡导建设资源节约型和环境友好型社会的今天,加大对废旧印刷电路板的资源化研究,有着特别重大的意义。通过对废旧PCB的组成成分和废旧PCB中金属的含量分析,指出废旧PCB具有很大的可再生利用价值。着重综述了废旧PCB资源化的常规用法,主要包括热处理法、化学处理法、和物理机械处理法,并对这些方法做了的分析归纳。通过对各种方法的综述可以看出采用物理机械方法回收废旧电路板应该是今后的发展方向。     

Micromechanical analysis of copper trace in printed circuit boards

Printed circuit boards (PCB) are designed and manufactured with a variety of polyamide materials such as solder mask, metallic material such as copper trace, composite materials such as prepreg and core material. Polyamide materials such as solder mask and composite materials such as prepreg play important factor on the total deformation of laminate package due to the large coefficient of thermal expansion (CTE). On the other hand, the patterning of the copper layers also exerts important influence to the thermal mechanical behavior of the substrate due to the consistent large Young’s modulus of copper at both room temperature and reflow temperature compared with the small Young’s modulus of polyamide materials. Some approximate methods based on rule of mixtures have been used for estimating material properties in layers of copper mixed with interlayer dielectric material, but few techniques include the effect of copper trace pattern. The detailed comparison of different approximate methods has been done in this paper and a modified homogenization method has been proposed to include the effect of copper trace pattern. A series of three point bending test are performed with the comparison of numerical prediction using the proposed homogenization method and the detailed copper trace pattern respectively. Finally, a micromechanical analysis is done for the copper trace crack problem in package-on-package (PoP).     

RF MEMS switches fabricated on microwave-laminate printed circuit boards

A novel fabrication process has been developed for directly constructing radio frequency microelectrical mechanical systems (RF MEMS) capacitive switches on microwave-laminate printed circuit boards (PCBs). The integrated process uses metal wet etching to form the metal lines for coplanar waveguides, compressive molding planarization (COMP) to planarize uneven surface heights for switch membrane formation, and high-density, inductively coupled plasma chemical vapor deposition (HDICP-CVD) for low-temperature silicon nitride deposition. This technology promises the potential of further monolithic integration with antennas on the same PCBs to form reconfigurable antennas without the concerns of mismatching among components.     

Layer assignment for printed circuit boards and integrated circuits

The layer assignment problem arises in printed circuit board (PCB) and integrated circuit (IC) design. It involves the assignment of interconnect wiring to various planes of a PCB or to various layers of interconnect wires in an IC. This paper reviews basic techniques for layer assignment in both PCBs and ICs. Two types of layer assignment are considered: (1) constrained layer assignment in which routing of interconnections is given and the objective is to assign wires to specific layers, and (2) unconstrained, or topological, layer assignment, in which both the physical routing of interconnections and assignment of the wires to layers is sought. Various objective functions, such as via minimization and minimization of signal delays through interconnect lines are discussed     

浅谈印制电路板信号损耗测试技术

在印制电路板设计、生产等过程中,传输线的信号损耗是板材应用性能的重要参数。信号损耗测试是印制电路板的信号完整性的重要表征手段之一。本文介绍了目前业界使用的几种PCB传输线信号损耗测量方法的原理和相关应用,并分析了其优势和限制。     

Finite difference modelling of moisture diffusion in printed circuit boards with ground planes

A finite difference model has been applied to diffusion modelling of molecular moisture diffusion in Printed Circuit Boards (PCB) that have ground planes. Capacitance measurements between two ground planes within a PCB during moisture uptake and removal allowed diffusion coefficients to be determined. These diffusion coefficients were then used to look at the effect of ground plane width, hole density and meshed ground plane dimensions on bake time. The effect of plating holes on the bake time has also been investigated. Results show that whilst a few hours are sufficient to bake PCBs with no ground planes, days, or even months are required to remove moisture from within ground planes due to the extra perpendicular distance the moisture must diffuse. The results demonstrate the importance of storage conditions of the PCB, as once moisture has diffused into a board with ground planes; it is often not feasible to remove it.     

On the external inductive coupling of differential signalling on printed circuit boards

A study of the common-mode radiation behavior of differential signalling is presented, considering small current imbalances, which may originate from differential driver phase skew and circuit asymmetries. Two configurations are investigated, a solid ground plane and a ground plane with an open slit as an example of a ground-plane discontinuity. The external coupling voltage responsible for common-mode radiation is quantified through coupling inductances, for which closed-form expressions are derived and numerically validated. It is found that common-mode electromagnetic interference from differential signalling may become comparable to conventional single trace routing when traces are placed near the edge of the ground plane. For traces routed across a ground-plane discontinuity, differential signalling is only an effective means for reducing radiation when signal imbalance can be kept small.