基于重叠栅工艺的硅量子点阵列的制备与调控

利用半导体量子点阵列结构实现近邻耦合是规模化扩展自旋量子比特的主要方案之一.随着量子点数目的增加,量子点阵列器件的制作工艺及参数调控均愈加复杂.本文介绍了一种重叠栅工艺结构,利用多层相互重叠且具有不同功能的栅极定义量子点,制作出结构紧凑、调控性好的量子点阵列器件,解决了工艺扩展的难题.此外,本文发展了一套高效可靠的调控方法,按顺序逐个添加量子点并建立虚拟电极,实现了对量子点参数的独立控制,并且能够高效且独立地调控各量子点中的电子数目,克服了大规模量子点阵列中电压参数配置的困难.这些方法为未来实现大规模自旋比特阵列提供了一种标准化的方案.     

库仑对数的量子修正

对D-He^3聚变产生的高能带电粒子，它们在本底等离子体中热化初始阶段的能量损失速率或慢化时间的计算准确性直接影响到能量平衡和快离子压强的计算结果。研究表明，在描述聚变产生的高能尾部粒子初始热化阶段。最好使用较精确的库仑对数lnAi，它们的二体库仑碰撞坦子力学效应不能忽视。     

自组织生长锗量子点的库仑荷电效应

将导纳谱应用于半导体ＧｅＳｉ量子点的研究，观察到了典型直径为１３ｎｍ的Ｇｅ量子点的库仑荷电效应及其分立能级结构．     

门电压控制的硅烯量子线中电子输运性质

硅烯是由单层硅原子形成的二维蜂窝状晶格结构,具有石墨烯类似的电学性质,由于硅烯中存在比较强的自旋轨道耦合而备受关注.本文利用非平衡格林函数方法研究了门电压控制的硅烯量子线中电子输运性质和能带结构.研究发现,只有在较强的门电压下,而且硅烯量子线具有较好的锯齿形或扶手椅形边界而不存在额外硅原子时,硅烯量子线中才存在无能隙的自旋极化边缘态.另外,计算结果表明这种门电压控制的硅烯量子线中边缘态在每个能谷处自旋是极化的.这些计算结果将为实验上利用电场制作硅烯纳米结构提供理论支持.     

四端双量子点系统中的自旋和电荷能斯特效应

基于非平衡态格林函数方法,理论研究了与四个电极耦合的双量子点系统中的自旋和电荷能斯特效应,考虑了不同电极的磁动量结构和量子点内以及量子点间电子的库仑相互作用对热电效应的影响.结果表明铁磁端口中的磁化方向能够有效地调节能斯特效应:当电极1和电极3中的磁化方向反平行排列时,通过施加横向的温度梯度,系统中将会出现纯的自旋能斯特效应;当电极4从普通金属端口转变为铁磁金属端口时,将同时观测到电荷和自旋能斯特效应.研究发现,能斯特效应对于铁磁电极极化强度的依赖程度较弱,但对库仑排斥作用十分敏感.在量子点内和点间库仑排斥作用的影响下,自旋及电荷能斯特系数有望提高两个数量级.     

多孔硅发光与量子尺寸效应的实验研究

利用电化学阳极腐蚀的方法制备了多孔硅膜,实验发现多孔硅膜为多层结构,表面层为纳米结构,其余为微米结构,多孔硅的物理及化学结构的研究表明多孔硅是一种表面上含硅、氧、氢、氟元素组成的化合物包覆着的纳米晶硅粒和微米硅丝.多孔硅的发光主要来自表面纳米结构层,亚微米结构层并未见发光,从实验上证实了多孔硅的发光与量子尺寸效应紧密关联.     

硅量子点的形状及其弯曲表面效应

硅量子点的弯曲表面引起系统的对称性破缺, 致使某些表面键合在能带的带隙中形成局域电子态.计算结果表明:硅量子点的表面曲率不同形成的表面键合结合能和电子态分布明显不同. 例如, Si–O–Si桥键在曲率较大的表面键合能够在带隙中形成局域能级, 而在硅量子点曲率较小的近平台表面上键合不会形成任何局域态, 但此时的键合结合能较低. 用弯曲表面效应(CS)可以解释较小硅量子点的光致荧光光谱的红移现象. CS效应揭示了纳米物理中又一奇妙的特性. 实验证实, CS效应在带隙中形成的局域能级可以激活硅量子点发光. 关键词： 硅量子点 弯曲表面效应 表面键合 局域能级     

有限深势阱下抛物量子线量子比特及其声子效应

采用Peaker变分法,研究了在有限深势阱下抛物量子线量子比特及其声子效应。量子线中这样的二能级体系可作为一个量子比特。当量子线中电子处于基态和第一激发态的叠加态时,电子的概率密度|ψ01(t,x,y,0)|2随着势阱宽度的增加而减小;电子的振荡周期T0随耦合强度α的增大而减小;振荡周期T0随受限长度l0的增加而增加。     

纳米硅量子线的发现与研究

一维纳米材料是当今介观物理学研究的前沿领域．文章报道了一种利用脉冲激光成功地制备纯度高、直径分布均匀的纳米硅量子线（ＳｉＮＷｓ）的方法，介绍了纳米量子线的形貌、显微结构、生长机理和物理性能研究的最新结果．纳米硅量子线的发现具有重要的科学意义和潜在的应用前景．     

电子在周期驱动耦合量子阱中的振荡

通过精确求解含时的量子体系，研究了在周期耦合驱动下电子在两量子阱中的受迫振荡.电 子在双量子阱间的隧穿可由周期性外场控制.得到了电子被囚禁在单一量子阱中的条件. 关键词： 量子阱 受迫振荡 周期驱动     

Electric-field-dependent charge delocalization from dopant atoms in silicon junctionless nanowire transistor

We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping(below 30 K) and nearest-neighbor hopping(above 30 K).The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source–drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K.     

An analytic model for gate-all-around silicon nanowire tunneling field effect transistors

An analytical model of gate-all-around(GAA) silicon nanowire tunneling field effect transistors(NW-TFETs) is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling(BTBT) efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane’s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.     

Transition from the Kondo effect to a Coulomb blockade in an electron shuttle

We investigate the effect of the mechanical motion of a quantum dot on the transport properties of a quantum dot shuttle.Employing the equation of motion method for the nonequilibrium Green’s function,we show that the oscillation of the dot,i.e.,the time-dependent coupling between the dot’s electron and the reservoirs,can destroy the Kondo effect.With the increase in the oscillation frequency of the dot,the density of states of the quantum dot shuttle changes from the Kondo-like to a Coulomb-blockade pattern.Increasing the coupling between the dot and the electrodes may partly recover the Kondo peak in the spectrum of the density of states.Understanding of the effect of mechanical motion on the transport properties of an electron shuttle is important for the future application of nanoelectromechanical devices.     

晶体硅太阳电池表面纳米线阵列减反射特性研究

为增强晶体硅太阳电池的光利用率, 提高光电转换效率, 研究了硅纳米线阵列的光学散射性质. 运用严格耦合波理论对硅纳米线阵列在310—1127 nm波段的反射率进行了模拟计算, 用田口方法对硅纳米线阵列的表面传输效率进行了优化. 结果表明, 当硅纳米线阵列的周期为50 nm, 占空比为0.6, 高度约1000 nm时减反射效果最佳; 该结构在上述波段的平均反射率约为2%, 且在较大入射角度范围保持不变. 采用金属催化化学腐蚀法, 于室温、室压条件下在单晶硅表面制备周期为60 nm,占空比为0.53, 高度为500 nm的硅纳米线阵列结构, 其反射率的实验测试结果与计算模拟值相符, 在上述波段的平均反射率为4%—5%, 相对于单晶硅35%左右的反射率, 减反射效果明显. 这种减反射微结构能够在降低太阳电池成本的同时有效减小单晶硅表面的光反射损失, 提高光电转换效率.     

碳纳米管包裹的硅纳米线复合结构的热稳定性研究

采用经典分子动力学方法模拟一定直径[111]晶向的硅纳米线填充不同扶手椅型单壁碳纳米管复合结构的加热过程, 通过可视化和能量分析的方法判断复合结构中硅纳米线和碳纳米管的热稳定性. 通过讨论碳纳米管的空间限制作用和分子间相互作用力的关系, 对碳纳米管和硅纳米线的热稳定性变化进行初步解释. 研究发现碳纳米管中硅纳米线的热稳定性和碳纳米管的直径关系密切: 当管径较小时, 硅纳米线的热稳定性有所提高, 当管径增大到一定大小时, 硅纳米线的热稳定性会突然显著地下降, 直到硅纳米线与管壁不存在分子间相互作用力, 硅纳米线的热稳定性才会恢复. 而硅纳米线填充到碳纳米管中对碳纳米管的热稳定性有着明显的降低作用.     

介观LC电路中的量子隧道效应

考虑到电子在纳米电容器中的运动是一个单电子隧穿过程,因而将电容器作为一个隧道结,应用隧道模型的稳态法,研究了介观LC电路中的电流电压特性.结果表明:由于库仑力的作用,介观LC电路中存在着阈值电压.当外加电压小于阈值电压时,隧穿电流为零,显示出库仑阻塞现象;当外加电压远大于阈值电压时,隧穿电流与电压成正比. 关键词： 介观LC电路 库仑阻塞 单电子隧道过程     

硅薄膜太阳电池表面纳米线阵列光学设计

陷光结构的优化是增加硅薄膜太阳电池光吸收进而提高其效率的关键技术之一. 以硅纳米线阵列为代表的光子晶体微纳陷光结构具有突破传统陷光结构Yablonovith极限的巨大潜力. 通常硅纳米线阵列可以用作太阳电池的增透减反层、轴向p-n结、径向p-n结. 针对以上三种应用, 本文运用有限时域差分(FDTD)法系统研究了硅纳米线阵列在 300-1100 nm 波段的光学特性. 结果表明, 当硅纳米线作为太阳电池的减反层时, 周期P=300 nm, 高度H=1.5 μm, 填充率(FR)为0.282条件下时, 反射率最低为7.9%. 当硅纳米线作为轴向p-n结电池时, P=500 nm, H=1.5 μm, FR=0.55条件下纳米线阵列的吸收效率高达22.3%. 硅纳米线作为径向p-n结电池时, 其光吸收主要依靠纳米线, 硅纳米线P=300 nm, H=6 μm, FR= 0.349 条件下其吸收效率高达32.4%, 进一步提高其高度吸收效率变化不再明显. 此外, 本文还分析了非周期性硅纳米线阵列的光学性质, 与周期性硅纳米线阵列相比, 直径随机分布和位置随机分布的硅纳米线阵列都可以使吸收效率进一步提高, 相比于周期性硅纳米线阵列, 优化后直径随机分布的硅纳米线阵列吸收效率提高了39%, 吸收效率为27.8%. 本文运用FDTD法对硅纳米线阵列的光学特性进行设计与优化, 为硅纳米线阵列在太阳电池中的应用提供了理论支持.     

Spatially‐resolved and polarized Raman scattering from a single Si nanowire

We report spatially‐resolved and polarized Raman scattering results from a single Si nanowire (NW). Transmission electron microscope images show that the surface morphology of the Si NW varies from smooth to rough along the long axis. As the NW grows, the smooth surface becomes rough because of Au diffusion to the surface, resulting in the formation of facets and stacking faults. Spatially‐resolved Raman spectra along the NW long axis reveal variations in tensile strain related to the morphological changes in NW surface. The tensile strain in the top segment of the NW with a smooth surface is greater than that in the bottom segment with a rough surface. Despite the formation of facets and stacking faults, polarized Raman scattering results both from the top and bottom segments of the NW are consistent with the Raman polarization selection rules expected for a cubic crystal. Copyright © 2015 John Wiley & Sons, Ltd.     

Drain-induced barrier lowering effect for short channel dual material gate 4H silicon carbide metal—semiconductor field-effect transistor

Sub-threshold characteristics of the dual material gate 4H-SiC MESFET (DMGFET) are investigated and the analytical models to describe the drain-induced barrier lowering (DIBL) effect are derived by solving one- and two- dimensional Poisson’s equations. Using these models, we calculate the bottom potential of the channel and the threshold voltage shift, which characterize the drain-induced barrier lowering (DIBL) effect. The calculated results reveal that the dual material gate (DMG) structure alleviates the deterioration of the threshold voltage and thus suppresses the DIBL effect due to the introduced step function, which originates from the work function difference of the two gate materials when compared with the conventional single material gate metal-semiconductor field-effect transistor (SMGFET).     

Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO₂ than SiO₂ in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, I_ON/I_OFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO₂, DIBL shows a reduction of 61.5% over SiO₂. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO₂ when compared to SiO₂. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO₂ based device. From the analysis, it is found that HfO₂ will be a better alternative for the future nanoscale device.