恒流应力下E2PROM隧道氧化层的退化特性研究

在电容测量的基础上研究了薄隧道氧化层在恒定Fowler-Nordheim(F-N)隧穿电流下的退化情况.这种退化是恒流应力和时间的函数,对恒流应力大小的依赖性更加强烈,隧道氧化层在F-N电流下的退化是注入电荷密度(Qinj)的函数.在较低Qinj下氧化层中发生正电荷俘获,在较高Qinj下发生负电荷俘获,导致栅压变化的反复.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明:热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

应力导致的薄栅氧化层漏电流瞬态特性研究

分别研究了FN隧穿应力和热空穴(HH)应力导致的薄栅氧化层漏电流瞬态特性.在这两种应力条件下,应力导致的漏电流(SILC)与时间的关系均服从幂函数关系,但是二者的幂指数不同.热空穴应力导致的漏电流中,幂指数明显偏离-1,热空穴应力导致的漏电流具有更加显著的瞬态特性.研究结果表明热空穴SILC机制是由于氧化层空穴的退陷阱效应和正电荷辅助遂穿中心的湮没.利用热电子注入技术,正电荷辅助隧穿电流可被大大地减弱.     

电压应力下超薄栅氧化层n-MOSFET的击穿特性

研究了90nm工艺下栅氧化层厚度为1.4nm的n-MOSFET的击穿特性，包括V-ramp(斜坡电压)应力下器件栅电流模型和CVS(恒定电压应力)下的TDDB(经时击穿)特性，分析了电压应力下器件的失效和退化机理.发现器件的栅电流不是由单一的隧穿引起，同时还有电子的翻越和渗透.在电压应力下，SiO₂中形成的缺陷不仅降低了SiO₂的势垒高度，而且等效减小了SiO₂的厚度(势垒宽度).另外，每一个缺陷都会形成一个导电通道，这些导电通道的形成增大了栅电流，导致器件性能的退化，同时栅击穿时间变长. 关键词： 超薄栅氧化层 斜坡电压 经时击穿 渗透     

具有纳米氧化层的磁性隧道结的热稳定性研究

研究发现在磁隧道结的反铁磁层和被钉扎铁磁层之间插入一层纳米氧化层，可以使磁隧道结的退火温度增加了40℃，即明显地提高了磁隧道结的温度稳定性.通过卢瑟福背散射实验直接观察到产生这一效应的原因是该纳米氧化层有效地抑制了Mn元素在退火过程中的扩散，从而使TMR值在较高的退火温度下得以保持. 关键词： 磁性隧道结 隧穿磁电阻 热稳定性 纳米氧化层     

薄栅氧化层中陷阱电荷密度的测量方法

提出了一种测量陷阱电荷密度的实验方法,该方法根据电荷陷落的动态平衡方程,利用恒流应力前后MOS电容高频CV曲线结合恒流应力下栅电压的变化曲线求解陷阱电荷密度及位置等物理量.给出了陷阱电荷密度的解析表达式和相关参数的提取方法和结果.实验表明这种方法方便而且具有较高的精度 关键词： 薄栅氧化膜 经时击穿 恒流应力 陷阱电荷密度     

Nb/AlOx-Al/Nb超导隧道结制备氧化工艺与特性研究

提出一种氧的等离子氧化的方法改善结区边缘绝缘性能,降低超导隧道结的漏电流。对Al膜进行等离子氧化能够有效的改善氧化膜的绝缘性能,AES分析表明:氧化绝缘层均匀,界面清晰;应用此方法成功制备出较好性能的Nb隧道结。     

ZrO2／SiO2多层膜中膜厚组合周期数及基底材料对残余应力的影响

ZrO₂／SiO₂多层膜由相同沉积条件下的电子束蒸发方法制备而成， 通过改变多层膜中高(ZrO₂)、低(SiO₂)折射率材料膜厚组合周期数的方法，研究了沉积 在熔石英和BK7玻璃 基底上多层膜中残余应力的变化. 用ZYGO光学干涉仪测量了基底镀膜前后曲率半径的变化， 并确定了薄膜中的残余应力. 结果发现，该多层膜中的残余应力为压应力，随着薄膜中膜厚 组合周期数的增加，压应力值逐渐减小. 而且在相同条件下，石英基底上所沉积多层膜中的 压应力值要小于BK7玻璃基底上所沉积多层膜中的压应力值. 用x射线衍射技术测量分析了膜 厚组合周期数不同的ZrO₂／SiO₂多层膜微结构，发现随着周期数增 加，多层膜的结晶程 度增强. 同时多层膜的微结构应变表现出了与所测应力不一致的变化趋势，这主要是由多层 膜中，膜层界面之间复杂的相互作用引起的. 关键词： 2／SiO₂多层膜')" href="#">ZrO₂／SiO₂多层膜 残余应力 膜厚组合周期数     

动态应力下超薄栅氧化层经时击穿的可靠性评价

实验发现动态电压应力条件下,由于栅氧化层很薄,高电平应力时间内隧穿入氧化层的电子与陷落在氧化层中的空穴复合产生中性电子陷阱,中性电子陷阱辅助电子隧穿.由于每个周期的高电平时间较短(远远低于电荷的复合时间),隧穿到氧化层的电子很少,同时低电平应力时间内一部分电荷退陷,形成的中性电子陷阱更少.随着应力时间的累积,中性电子陷阱达到某个临界值,栅氧化层突然击穿.高电平时形成的陷阱较少和低电平时一部分电荷退陷,使得器件的寿命提高. 关键词： 超薄栅氧化层 斜坡电压 经时击穿     

磁控溅射制备的W，WSi2, Si单层膜和W/Si,WSi2/Si多层膜应力

采用直流磁控溅射技术制备了厚度约100 nm的W,WSi2,Si单层膜和周期约为20 nm,Si膜层厚度与周期的比值为0.5的W/Si,WSi2/Si周期多层膜。利用台阶仪对镀膜前后基底表面的面形进行了测试,计算并比较了不同膜系的应力值。结果表明：W单层膜表现出较大的压应力,而W/Si周期膜则表现为张应力。WSi2单层膜和WSi2/Si周期多层膜均表现为压应力,没有应力突变,应力特性最为稳定。因此,WSi2/Si材料组合是研制大膜对数X射线多层膜较好的材料组合。     

Low voltage substrate current： a monitor for interface states generation in ultra-thin oxide n-MOSFETs under constant voltage stresses

The low voltage substrate current （Ib） has been studied based on generation kinetics and used as a monitor of interface states （Nit） generation for ultra-thin oxide n-MOSFETs under constant voltage stress. It is found that the low voltage Ib is formed by electrons tunnelling through interface states, and the variations of Ib（△Ib） are proportional to variations of Nit （△Nit）. The Nit energy distributions were determined by differentiating Nit（Vg）. The results have been compared with that measured by using gate diode technique.[第一段]     

The conduction mechanism of stress induced leakage current through ultra-thin gate oxide under constant voltage stresses

The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.     

开态应力下电压和电流对AlGaN/GaN高电子迁移率晶体管的退化作用研究

通过采集等功率的两种不同开态直流应力作用下AlGaN/GaN高电子迁移率晶体管(HEMTs)漏源电流输出特性、源区和漏区大信号寄生电阻、转移特性、阈值电压随应力时间的变化, 并使用光发射显微镜观察器件漏电流情况, 研究了开态应力下电压和电流对AlGaN/GaN高电子迁移率晶体管的退化作用. 结果表明, 低电压大电流应力下器件退化很少, 高电压大电流下器件退化较明显. 高电压是HEMTs退化的主要因素, 栅漏之间高电场引起的逆压电效应对参数的永久性退化起决定性作用. 除此之外, 器件表面损坏部位的显微图像表明低电压大电流下器件失效是由于局部电流密度过高, 出现热斑导致器件损伤引起的.     

Degradation of the transconductance of gate-modulated generation current in nMOSFET

The degradation of transconductance (G) of gate-modulated generation current I_GD in LDD nMOSFET is investigated. The G curve shifts rightward under the single electron-injection-stress (EIS). The trapped electrons located in the gate oxide over the LDD region (Q_L) makes the effective drain voltage minish. Accordingly, the G peak in depletion (G_MD) and that in weak inversion (G_MW) decrease. It is found that Δ G_MD and Δ G_MW each have a linear relationship with the n-th power of stress time (tⁿ) in dual-log coordinate: Δ G_MD ∝ tⁿ, Δ G_MD ∝ tⁿ (n=0.25). During the alternate stress, the injected holes neutralize Q_L induced by the previous EIS. This neutralization makes the effective V_D restore to the initial value and then the I_GD peak recovers completely. Yet the threshold voltage recovery is incomplete due to the trapped electron located over the channel (Q_C). As a result, G_MW only recovers to the circa 50% of the initial value after the hole-injection-stress (HIS). Instead, G_MD is almost recovered. The relevant mechanisms are given in detail.     

Progressive current degradation and breakdown behavior in GaN LEDs under high reverse bias stress

The progressive current degradation and breakdown behaviors of GaN-based light emitting diodes under high reversebias stress are studied by combining the electrical, optical, and surface morphology characterizations. The current features a typical "soft breakdown" behavior, which is linearly correlated to an increase of the accumulative number of electroluminescence spots. The time-to-failure for each failure site approximately obeys a Weibull distribution with slopes of about 0.67 and 4.09 at the infant and wear-out periods, respectively. After breakdown, visible craters can be observed at the device surface as a result of transient electrostatic discharge. By performing focused ion beam cuts coupled with scan electron microscope, we observed a local current shunt path in the surface layer, caused by the rapid microstructure deterioration due to significant current heating effect, consistent well with the optical beam induced resistance change observations.     

Degradation of the transconductance of a gate-modulated generation current in nMOSFET

The degradation of transconductance(G) of a gate-modulated generation current I GD in a LDD nMOSFET is investigated.The G curve shifts rightward under the single electron-injection-stress(EIS).The trapped electrons located in the gate oxide over the LDD region(QL) makes the effective drain voltage diminish.Accordingly,the G peak in depletion(GMD) and that in weak inversion(GMW) decrease.It is found that △GMD and △GMW each have a linear relationship with the n-th power of stress time(tn) in a dual-log coordinate:△G MD∝tn,△GMD∝tn(n=0.25).During the alternate stress,the injected holes neutralize QL induced by the previous EIS.This neutralization makes the effective V D restore to the initial value and then the I GD peak recovers completely.Yet the threshold voltage recovery is incomplete due to the trapped electron located over the channel(QC).As a result,G MW only recovers to circa 50% of the initial value after the hole-injection-stress(HIS).Instead,G MD almost recovers.The relevant mechanisms are given in detail.     

拉伸应力下的高温超导带材临界电流特性研究

针对在低温、拉伸应力共同作用下,高温超导带材临界电流测量困难的问题,详细介绍了一种独立改造后的简便拉伸设备,利用四引线法对两种具有代表性的高温超导带材的临界电流进行了测量,并对结果进行了一系列的验证,证明了此设备能较好的完成测量任务。最后,结合带材的物理结构,简要分析了临界电流产生变化的原因。对今后的测量工作和超导磁体的设计与制备有一定的指导意义。     

Growth, microstructure and electrical properties of sputter-deposited hafnium oxide (HfO2) thin films grown using a HfO2 ceramic target

Hafnium oxide (HfO₂) thin films have been made by radio-frequency (rf) magnetron-sputtering onto Si(1 0 0) substrates under varying growth temperature (T_s). HfO₂ ceramic target has been employed for sputtering while varying the T_s from room temperature to 500 °C during deposition. The effect of T_s on the growth and microstructure of deposited HfO₂ films has been studied using grazing incidence X-ray diffraction (GIXRD), and high-resolution scanning electron microscopy (HR-SEM) coupled with energy dispersive X-ray spectrometry (EDS). The results indicate that the effect of T_s is significant on the growth, surface and interface structure, morphology and chemical composition of the HfO₂ films. Structural characterization indicates that the HfO₂ films grown at T_s < 200 °C are amorphous while films grown at T_s > 200 °C are nanocrystalline. An amorphous-to-crystalline transition occurs at T_s = 200 °C. Nanocrystalline HfO₂ films crystallized in a monoclinic structure with a (−1 1 1) orientation. An interface layer (IL) formation occurs due to reaction at the HfO₂-Si interface for HfO₂ films deposited at T_s > 200 °C. The thickness of IL increases with increasing T_s. EDS at the HfO₂-Si cross-section indicate that the IL is a (Hf, Si)-O compound. The electrical characterization using capacitance-voltage measurements indicate that the dielectric constant decreases from 25 to 16 with increasing T_s. The current-voltage characteristics indicate that the leakage current increases significantly with increasing T_s due to increased ILs.     

AlGaN/GaN 高电子迁移率晶体管漏电流退化机理研究

本文首先制备了与AlGaN/GaN高电子迁移率晶体管 (HEMT) 结构与特性等效的AlGaN/GaN异质结肖特基二极管, 采用步进应力测试比较了不同栅压下器件漏电流的变化情况, 然后基于电流-电压和电容-电压测试验证了退化前后漏电流的传输机理, 并使用失效分析技术光发射显微镜 (EMMI) 观测器件表面的光发射, 研究了漏电流的时间依赖退化机理. 实验结果表明: 在栅压高于某临界值后, 器件漏电流随时间开始增加, 同时伴有较大的噪声. 将极化电场引入电流与电场的依赖关系后, 器件退化前后的 log(I_FT/E)与√E 都遵循良好的线性关系, 表明漏电流均由电子Frenkel-Poole (FP) 发射主导. 退化后 log(I_FT/E)与√E 曲线斜率的减小, 以及利用EMMI在栅边缘直接观察到了与缺陷存在对应关系的“热点”, 证明了漏电流退化的机理是: 高电场在AlGaN层中诱发了新的缺陷, 而缺陷密度的增加导致了FP发射电流I_FT的增加. 关键词： AlGaN/GaN 高电子迁移率晶体管 漏电流 退化机理