Hot-carrier-stress effects on gate-induced drain leakage current inn-channel MOSFETs

The effects of hot-carrier stress on gate-induced drain leakage (GIDL) current in n-channel MOSFETs with thin gate oxides are studied. It is found that the effects of generated interface traps (ΔD _it) and oxide trapped charge on the GIDL current enhancement are very different. Specifically, it is shown that the oxide trapped charge only shifts the flat-band voltage, unlike ΔD _it. Besides band-to-band (B-B) tunneling, ΔD _it introduces an additional trap-assisted leakage current component. Evidence for this extra component is provided by hole injection. While trapped-charge induced leakage current can be eliminated by a hole injection subsequent to stress, such injection does not suppress interface-trap-induced leakage current     

Asymmetric gate-induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance

Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from -50 to 200/spl deg/C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain-body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical <110> pillar sidewalls and the horizontal <100> wafer surface.     

Modelling of gate-induced drain leakage in relation to technological parameters and temperature

The junction breakdown of a MOS transistor with thin gate oxide, imposed undesirable problems. This phenomenon is attributed, particularly, to band-to-band tunnelling occurring in the gate-to-drain overlap region. This is the source of a gate-induced drain leakage (gidl) current I_gidl, limiting therefore the further MOSFET scaling. In this paper we ara interested in the modelling of this current. The model is used to investigate the influence of the technological parameters and the temperature on I_gidl current characteristics.     

Design for suppression of gate-induced drain leakage in LDD MOSFETsusing a quasi-two-dimensional analytical model

A systematic study of gate-induced drain leakage (GIDL) in single-diffusion drain (SD), lightly doped drain (LDD), and fully gate-overlapped LDD (GOLD) NMOSFETs is described. Design curves quantifying the GIDL dependence on gate oxide thickness, phosphorus dose, and spacer length are presented. In addition, a new, quasi-2-D analytical model is developed for the electric field in the gate-to-drain overlap region. This model successfully explains the observed GIDL dependence on the lateral doping profile of the drain. Also, a technique is proposed for extracting this lateral doping profile using the measured dependence of GIDL current on the applied substrate bias. Finally, the GIDL current is found to be much smaller in lightly doped LDD devices than in SD or fully overlapped LDD devices, due to smaller vertical and lateral electric fields. However, as the phosphorus dose approaches 10¹⁴/cm², the LDD and fully overlapped LDD devices exhibit similar GIDL current     

Impact of interface traps on gate-induced drain leakage current in n-type metal oxide semiconductor field effect transistor

As the features sizes of metal oxide semiconductor field effect transistor (MOSFET) are aggressively scaled into the submicron domain, hot carriers generated by the very large electric fields of drain region create serious reliability problems for the integrated circuit in MOS technology. The charges trapping in the gate oxide and the defects at the Si/SiO₂ interface have also undesirable effects on the degradation and ageing of MOSFET. Among the problems caused by these effects is the band-to-band tunnelling (BBT) of hot carriers in the gate-to-drain overlap region which is the source of the gate-induced drain leakage current I _gidl. The oxide charges shift the flat-band voltage and result in an enhancement of the I _gidl current. On the other hand, the generation of interface traps introduce an additional band-trap-band (BTB) leakage mechanism and lead to a significant increase ?I _gidl in a drain leakage current. In this work we propose a new method to calculate the I _gidl current which takes into account of the BTB leakage mechanism in order to clarify the impact of interface traps located in the gate-to-drain overlap region on the I _gidl current.     

Interface trap-enhanced gate-induced leakage current in MOSFET

Interface traps are shown to significantly affect the gate-induced drain-leakage current in a MOSFET or gated diode. The leakage current in a p⁺-gated diode can increase by two orders of magnitude when the interface trap density is increased from 10¹¹ to 10¹² cm^-2-eV^-1. The fact that thermal annealing at 300°C can eliminate both the generated interface traps and the excessive leakage current supports the close correlation between the two. The p⁺-gated diode is found to be more susceptible to this interface-trap related leakage current than the n⁺-device, which can be explained qualitatively by an interface-trap-assisted tunneling model     

Comparison of gate-induced drain leakage and charge pumpingmeasurements for determining lateral interface trap profiles inelectrically stressed MOSFETs

Improved methods for extracting lateral spatial profiles of interface traps in electrically stressed MOSFETs from gate-induced drain leakage and charge pumping measurements are proposed. Simplified theoretical models are developed. The formal similarity of the two methods is shown. The results obtained on submicron MOSFET after uniform (Fowler-Nordheim) and nonuniform (hot carrier) stress are compared and found to be in good agreement. The relative merits of these techniques are discussed     

Hot-carrier-induced off-state current leakage in submicrometerPMOSFET devices

Hot-carrier-induced off-state leakage (HCIOL) currents were successfully used as a new monitor in characterizing device reliability. HCIOL current increases drastically with reducing channel length, but the stress bias only affects the onset time of HCIOL current. For buried-channel PMOSFET's, only the HCIOL currents at the reverse measurement configuration were dominant. However, in surface-channel devices, HCIOL currents at both forward and reverse configurations became important. An empirical HCIOL current model was developed to quantify device lifetime as a function of channel length and stress voltage. Estimated lifetime results indicated that HCIOL current will impose a major limit on device reliability especially for deep-submicrometer technology and low power applications     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

DC pulse hot-carrier-stress effects on gate-induced drain leakagecurrent in n-channel MOSFETs

The DC pulse hot-carrier-stress effects on the degradation in gate-induced drain leakage (GIDL) current in nMOSFETs in a high field regime and the mechanisms of stress-induced degradation are studied. In this paper, we investigate DC pulse stress parameters in GIDL which include frequency, rise/fall time, and stressing pulse amplitude. The contributions of hot-hole injection, interface state generation, and hot-electron injection in a period of transient stress are identified. It is found that the device degradation increases with increased pulse frequency under maximum gate current stress, while it decreases with reduced pulse frequency under maximum substrate current stress. This work is useful for DC pulse hot-carrier-stress reliability analysis under circuit operation     

Improved GeOI substrates for pMOSFET off-state leakage control

The origin of parasitic leakage that occurs in some GeOI pMOSFETs has been investigated and located at the Ge-buried oxide (BOX) interface. Silicon passivation of that interface was found to be effective in reducing this current. An optimum thickness of the buried silicon capping is required to reduce the parasitic leakage current while preserving Ge-like back channel transport properties.     

Subbreakdown drain leakage current in MOSFET

Significant drain leakage current can be detected at drain voltages much lower than the breakdown voltage. This subbreakdown leakage can dominate the drain leakage current at zero VGin thin-oxide MOSFET's. The mechanism is shown to be band-to-band tunneling in Si in the drain/gate overlap region. In order to limit the leakage current to 0.1 pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 2.2 MV/cm. This may set another constraint for oxide thickness or power supply voltage.     

Modeling of drain leakage current in SOI pMOSFETs

In this paper we present a compact drain leakage current model for fully-depleted (FD) SOI pMOSFETs. The analytical and physics-based model was developed using a quasi-two dimensional approach, in which the longitudinal and vertical surface channel electric fields can be calculated. It can be used to accurately calculate drain leakage current as a function of drain and gate biases. This model in conjunction with our previous published subthreshold and above threshold model forms a concrete drain current model for FD SOI pMOSFET operation in off and on states.     

Subthreshold drain leakage currents in MOS field-effect transistors

There are two contributions to the drain-source leakage current in MOS field-effect transistors for gate voltages below the extrapolated threshold voltage (Vtx) : 1) reverse-bias drain junction leakage current, and 2) a surface channel current that flows when the surface is weakly inverted. Nearly six orders of magnitude of drain-source current from the background limit imposed by the drain junction leakage to the lower limits of detection of most curve tracers (0.05 µA) are controlled by gate-source voltages below the extrapolated threshold voltage. It is shown that this current flows only for gate voltages above the intrinsic voltage Vi, the gate voltage at which the silicon surface becomes intrinsic. For gate voltages between Viand Vtxthe surface is weakly inverted with the resulting channel conductivity being responsible for the drain-source current "tails" observed for gate voltages below Vtx. The importance of the intrinsic voltage in designing low-leakage CMOS and standard PMOS circuitry is discussed.     

Suppression of parasitic bipolar effects and off-state leakage infully-depleted SOI n-MOSFET's using Ge-implantation

This work demonstrates a well-controlled technique of channel defect engineering, by implanting germanium into the channel of a Silicon-On-Insulator (SOI) MOSFET to generate subgap energy states. These subgap states act as minority-carrier lifetime killers to spoil the parasitic bipolar gain, and thus improve the source-to-drain breakdown voltage and reduce the front-channel gate-induced-drain-leakage (GIDL). The Ge-implant also serves the dual purpose of positioning most of the subgap states in the back interface region which reduce back-channel off-state leakage     

Dynamic Turn-On Mechanism of the n-MOSFET Under High-Current Stress

In this letter, the dynamic turn-on mechanism of the n-MOSFET under high-current-stress event is investigated by using a real-time current and voltage measurement. Results reveal the existence of ldquoself-consistent effect,rdquo i.e., the turn-on region of the parasitic n-p-n bipolar can change from one region to another region and increases with the stress current (ID). Furthermore, experimental data show that the minimum substrate potential to sustain a stable snapback phenomenon is 0.9 V and increases with ID instead of 0.6-0.8 V and independent of ID as reported in early literatures.     

Testing and diagnostics of CMOS circuits using light emission from off-state leakage current

In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others.     

Enhanced off-state leakage currents in n-channel MOSFETs withN2O-grown gate dielectric

This paper reports on the off-state drain (GIDL) and gate current (Ig) characteristics of n-channel MOSFETs using thin thermal oxide (OX), N₂O-nitrided oxide (N2ON), and N₂O-grown oxide (N20G) as gate dielectrics. Important phenomena observed in N20G devices are enhanced GIDL and Ig in the low-field region as compared to the OX and N20N devices. They are attributed to heavy-nitridation-induced junction leakage and shallow-electron-trap-assisted tunneling mechanisms, respectively. Therefore, N2ON oxide is superior to N20G oxide in leakage-sensitive applications     

Impact of gate induced drain leakage on overall leakage ofsubmicrometer CMOS VLSI circuits

In this paper, the impact of gate induced drain leakage (GIDL) on the overall leakage of submicrometer VLSI circuits is studied. GIDL constitutes a serious constraint, with regards to off-state current, in scaled down complimentary metal-oxide-semiconductor (CMOS) devices for DRAM and/or EEPROM applications. Our research shows that the GIDL current is also a serious problem in scaled CMOS digital VLSI circuits. We present the experimental and simulation data of GIDL current as a function of 0.35-μm CMOS technology parameters and layout of CMOS standard cells. The obtained results show that a poorly designed standard cell library for VLSI application may result in extremely high leakage current and poor yield     

Mechanisms of interface trap-induced drain leakage current inoff-state n-MOSFET's

An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model, a complete band-trap-band leakage path is formed at the Si/SiO₂ interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 μm n-MOSFET was subjected to a dc voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsibility for the leakage current at a large drain-to-gate bias (V_dg). The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression ΔI_d=Aexp(B_it/F). The value of B_it about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V_dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V_dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant