共查询到18条相似文献,搜索用时 62 毫秒
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本文报道了薄膜SIMOX/SOI材料上全耗尽MOSFET的制备情况,并对不同硅膜厚度和不同背面栅压下的器件特性进行了分析和比较.实验结果表明,全耗尽器件完全消除了"Kink"效应,低场电子迁移率典型值为620cm2/V·s,空穴迁移率为210cm2/V·s,泄漏电流低于10-12A;随着硅膜厚度的减簿,器件的驱动电流明显增加,亚阈值特性得到改善;全耗尽器件正、背栅之间有强烈的耦合作用,背表面状况可以对器件特性产生明显影响.该工作为以后薄膜全耗尽SIMOX/SOI电路的研制与分析奠定了基础. 相似文献
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The impact of quantum confinement on the electrical characteristics of ultrathin-channel GeO1 n- MOSFETs is investigated on the basis of the density-gradient model in TCAD software. The effects of the channel thickness (Tch) and back-gate bias (Vbg) on the electrical characteristics of GeOI MOSFETs are examined, and the simulated results are compared with those using the conventional semi-classical model. It is shown that when T~h 〉 8 rim, the electron conduction path of the GeOI MOSFET is closer to the front-gate interface under the QC model than under the CL model, and vice versa when Tch 〈 8 rim. Thus the electrically controlled ability of the front gate of the devices is influenced by the quantum effect. In addition, the quantum-mechanical mechanism will enhance the drain-induced barrier lowering effect, increase the threshold voltage and decrease the on-state current; for a short channel length (≤ 30 nm), when Tch 〉 8 nm (or 〈 8 nm), the quantum-mechanical mechanism mainly impacts the subthreshold slope (or the threshold voltage). Due to the quantum-size effect, the off-state current can be suppressed as the channel thickness decreases. 相似文献
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The influences of the main structure and physical parameters of the dual-gate GeOl MOSFET on the device performance are investigated by using a TCAD 2D device simulator. A reasonable value range of germanium (Ge) channel thickness, doping concentration, gate oxide thickness and permittivity is determined by analyzing the on-state current, off-state current, short channel effect (SCE) and drain-induced barrier lowering (DIBL) effect of the GeOI MOSFET. When the channel thickness and its doping concentration are 10-18 nm and (5-9)×1017 cm-3, and the equivalent oxide thickness and permittivity of the gate dielectric are 0.8-1 nm and 15-30, respectively, excellent device performances of the small-scaled GeOI MOSFET can be achieved: on-state current of larger than 1475 μA/μm, off-state current of smaller than 0.1μA/μm, SCE-induced threshold-voltage drift of lower than 60 mV and DIBL-induced threshold-voltage drift of lower than 140 mV. 相似文献
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晶圆超薄磨片工艺是为减小功率开关管导通电阻,工艺中存在超薄晶圆磨片后转运过程中破片及超薄晶圆背面蒸镀金属等问题.现有的晶圆磨片的一般厚度为200μm,超薄磨片的目标是100μm.本研究采用同一批次晶圆,分批,2片超薄研磨,其他采用正常工艺减薄,封装测试条件相同.对比封装测试完毕的器件的导通电阻,超薄研磨器件的导通电阻减小约10%. 相似文献
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采用自洽解方法求解一维薛定谔方程和二维泊松方程,得到电子的量子化能级和相应的浓度分布,利用MWKB方法计算电子隧穿几率,从而得到不同栅偏置下超薄栅介质MOSFET的直接隧穿电流模型。一维模拟结果与实验数据十分吻合,表明了模型的准确性和实用性。二维模拟结果表明,低栅压下,沟道边缘隧穿电流远大于沟道中心隧穿电流,沟道各处的隧穿电流均大于一维模拟结果;高栅压下,隧穿电流在沟道的分布趋于一致,且逼近一维模拟结果。 相似文献
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8英寸(1英寸=2.54 cm)薄层硅外延片的不均匀性是制约晶圆芯片良率水平的瓶颈之一.研究了硅外延工艺过程中影响薄外延层厚度和电阻率均匀性的关键因素,在保证不均匀性小于3%的前提下,外延层厚度和电阻率形成中间低、边缘略高的“碗状”分布可有效提高晶圆的良率水平.通过调整生长温度和氢气体积流量可实现外延层厚度的“碗状”分布,但调整温区幅度不得超过滑移线的温度门槛值.通过提高边缘温度来提高边缘10 mm和6 mm的电阻率,同时提高生长速率以提高边缘3 mm的电阻率,获得外延层电阻率的“碗状”分布,8英寸薄层硅外延片的的边缘离散现象得到明显改善,产品良率也有由原来的94%提升至98.5%,进一步提升了8英寸薄层硅外延片产业化良率水平. 相似文献
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提出了一种基于负阻器件共振隧穿二极管(RTD)与MOSFET结合的新型压控振荡器(VCO),并利用了高级设计系统(ADS)软件对该振荡器的可行性进行了电路仿真,利用分立RTD、MOSFET器件实现了此种VCO,实际调频范围在20~26 MHz之间。RTD与三端器件的连接方式不同可呈现不同的调制I-V特性,这种调制特性对基于RTD的振荡电路的频率也会产生影响。通过深入研究这种调制对振荡电路频率产生的影响,得到多种不同于常规方法的电压控制频率方式,其中一些具有很好的线性度。因此该电路的研究对于RTD在高频、高速振荡电路中的进一步应用具有重要意义。 相似文献
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Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate 总被引:1,自引:1,他引:1
Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm= N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices. 相似文献
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在对植物信息系统的开发设计过程中,提出了结合即时通讯技术,同时弥补C/S与B/S混合结构缺陷的新软件架构D/S(Desktop/Server),并以D/S为框架,建立即时型植物信息系统模型.通过对该模型中各模块的作用及相互关系的分析,阐述了业务流程与数据建模相结合的设计出发点,并通过对系统结构及主要技术实现的剖析,进一步说明该设计方案的优越性和实用性. 相似文献