A 5-Gbps Test System for Wafer-Level Packaged Devices

This paper describes an economical approach to high-speed testing of wafer-level packaged logic devices. The solution assumes that the devices have built-in self-test features, thereby reducing the complexity of external test instrumentation required. A stand-alone miniature tester is connected to the top of a wafer probe card, transmitting and receiving multiple high-speed (2–5 Gbps) signals. To keep costs low, the tester uses off-the-shelf components. However, its performance in some respects exceeds that of traditional automated test equipment (ATE). Measurements demonstrate the tester producing 5-Gbps signals with a $pm$ 18-ps timing accuracy. The generated signals exhibit low jitter ($sim$35 ps) and have a rise time of about 60 ps. Similar performance is also shown for signal capture.      

A Novel Wafer-Level Hermetic Packaging for MEMS Devices

Some emerging microelectromechanical systems (MEMS) devices such as high-performance inertial sensors and high-speed actuators must be operated in a high vacuum and in order to create this vacuum environment, specific packaging is required. To satisfy this demand, this paper presents a novel method for hermetic and near-vacuum packaging of MEMS devices. We use wafer-level bonding technology to combine with vacuum packaging, simultaneously. For this packaging solution, the wafers with air-guided micro-through-holes were placed on a custom-built design housed in a vacuum chamber maintained at a low-pressure environment of sub-10 mtorr. Packaging structure is then sealed by solder ball reflow process with the lower heating temperature of 300degC to fill up micro-through-hole. Experimental results shown the hermetical packaging technique using solder sealing is adapted to the wafer-level microfabrication process for MEMS devices and can achieve better yield and performance. Thus, this technique is very useful for many applications with high performance and low packaging cost can be obtained due to wafer-level processing.     

适应微节距元器件的自动化装配

随着封装和引脚数量的激增,对产品生产制造商而言,面临着新的和不断增加的压力。对于微节距元器件来说有着一系列的挑战。自动化的元器件操作设备在提高改善生产制造效率的同时,有助于确保元器件的完整性。     

微细间距PCB装配的测试考虑

倒装芯片和芯片规模封装对微细间距PCB组件的装配厂商提出了特殊的挑战。为此推动着测试解决方法不断的向前发展,以确保能够跟上这些新型封装技术发展的步伐。由于特征尺寸不断缩小、电路测试点受到限制和缺乏观察点的问题,将通过新的测试工具,包括边界扫描、声致显微扫描和自动化X光射线检测来予以克服。     

细间距器件焊点桥接研究

根据能量最小原理建立SMT焊点形态预测的三维数学模型,模拟了焊点桥接成形过程并对模拟结果进行实验验证。通过分析模拟结果,对SMT焊点钎料桥接机理进行理论研究。     

Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging

In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a $J$-shaped spring design produces a combination of high 3-D compliances and acceptable electrical parasitics. Further, numerical analyses on the $J$ -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 $mu{rm m}$ ). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to $sim$35 GHz without significant power loss.      

倒装芯片封装器件开封方法研究

对倒装芯片封装(Flip-Chip Package)器件开封技术进行了研究。总结了倒装芯片封装的类型、结构和封装材料；从理论上证明了倒装芯片封装器件开封的可能,并找出了限制开封的制约因素；提出了一种倒装芯片封装器件开封方法,通过X射线检查、镶嵌、磨抛和酸刻蚀的综合应用,突破了限制这类器件开封的因素,并证明了该方法的适用性；给出了建议的试验条件,并展示了开封效果。     

Design Optimization of Needle Geometry for Wafer-Level Probing Test

The probing test is a typical quality control method for individual chips on a wafer. With a proper design, the service life of probing needles in the probe card can be sufficiently elongated and hence reduces the testing cost. In this paper, we followed the Taguchi method with the $L_{18}(2^{1}times 3^{7})$ orthogonal array to obtain an optimal geometrical design of the probing needle based on the minimization of the scrub length the probe tip travels during a wafer-level probing test procedure. Geometrical factors of the needle included tip shape, needle diameter, beam length, taper length, knee diameter, shooting angle, tip length, and tip diameter. Importance of theses factors on the scrub length was also ranked.      

Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In

Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significant power variations in a die during test-pattern application. This variation adversely affects the accuracy of predictions of junction temperatures and the time required for burn-in. We present a test-pattern ordering technique for WLTBI, where the objective is to minimize the variation in power consumption during test application. The test-pattern ordering problem for WLTBI is formulated and solved optimally using integer linear programming. Efficient heuristic methods are also presented to easily solve the pattern-ordering problem for large circuits. Simulation results are presented for the ISCAS'89 and the IWLS'05 benchmark circuits, and the proposed ordering technique is compared with two baseline methods that carry out pattern ordering to minimize peak power and average power, respectively. A third baseline method that randomly orders test patterns is also used to evaluate the proposed methods.      

Novel Nano-Scale Conductive Films With Enhanced Electrical Performance and Reliability for High Performance Fine Pitch Interconnect

In this paper, a novel nano-scale conductive film which combines the advantages of both traditional anisotropic conductive adhesives/films (ACAs/ACFs) and nonconductive adhesives/films (NCAs/NCFs) is introduced for next generation high-performance ultra-fine pitch packaging applications. This novel interconnect film possesses the properties of electrical conduction along the $z$ direction with relatively low bonding pressure (ACF-like) and the ultra-fine pitch $({≪ 30}~ mu {rm m})$ capability (NCF-like). The nano-scale conductive film also allows a lower bonding pressure than NCF to achieve a much lower joint resistance (over two orders of magnitude lower than typical ACF joints) and higher current carrying capability. With low temperature sintering of nano-silver fillers, the joint resistance of the nano-scale conductive film was as low as $10 ^{-5}~{rm Ohm}$. The reliability of the nano-scale conductive film after high temperature and humidity test (85$^{circ}{rm C}$/85% RH) was also improved compared to the NCF joints. The insertion loss of nano-scale conductive film joints up to 10 GHz was almost the same as that of the standard ACF or NCF joints, suggesting that the nano-scale conductive film is suitable for reliable high-frequency adhesive joints in microelectronics packaging.      

密脚间距QFP集成电路引线成形工艺研究

集成电路引线成形原本是集成电路封装的后道工序,成形质量将直接影响电子装联产品的可靠性,其关键工艺点在于成形的肩宽、站高、焊接长度和共面度等关键工艺参数的选择以及成形工艺装备的合理配置与优化.论述了目前表面贴装密脚间距QFP封装器件在应用中遇到的引线成形问题,介绍了该类器件成形中的相关技术要求及目前国内外器件成形的现状,提出了引线手工成形的解决方案.     

面向家庭局域网设备的新型架构

在配备了能源利用领域的最新技术成果之后,家庭局域网(HAN)开始准备取代传统的家电生态系统.本文介绍了HAN设备体系架构,该架构不仅与家庭局域网无缝集成,还可以充当低成本的电表,监控电气设备的电能消耗和运行.     

一种声表面波器件的新型晶圆级封装技术

总结了声表面波(SAW)器件传统封装技术中存在的问题,提出了一种SAW器件新型晶圆级封装技术。采用一种有机物干膜,分别经两次压膜、曝光和显影完成了对SAW芯片在划片前的封装,并用实验进行了验证。实验结果表明,本技术具有在不改变叉指换能器(IDT)质量负载的情况下同时具备吸声的功能,改善器件的带外抑制能力,增强了产品的一致性和可靠性。本技术在SAW器件的封装方面有广阔的应用前景。     

面向窄节距倒装互连的预成型底部填充技术

近年来随着电子产品的小型化发展,窄节距倒装芯片互连已经成为研究热点。传统的倒装芯片组装后底部填充技术(例如底部毛细填充)在用于窄节距互连时易产生孔洞,导致可靠性降低,因此产业界开发了面向窄节距倒装芯片互连的预成型底部填充技术,主要包括非流动底部填充和圆片级底部填充。介绍了这类新型底部填充技术的具体工艺及材料需求,并提出了目前其在大规模量产以及未来更窄节距应用中存在的问题及挑战,总结了目前产业界在提高量产生产效率、提升电互连的可靠性以及开发纳米级高热导率填料等方面提出的解决方案,分析了该技术未来的发展方向。     

微波功率器件的扇形线测试电路

在微波电路原理和半导体器件物理的基础上,设计和模拟了两种用于微波功率器件的测试电路,并且设计了与之配套的测试夹具.采用矢量网络分析仪对该测试电路和夹具在3～8GHz范围内进行了小信号测试.模拟和测试结果都表明,采用扇形线的测试电路性能较好.最后采用该电路和夹具对C波段AlGaN/GaN HEMT微波功率器件进行了微波功率测试,测试频率为5.4GHz.实验测得最大功率增益为8.75dB,最大输出功率为33.2dBm.     

微波功率器件的扇形线测试电路

在微波电路原理和半导体器件物理的基础上,设计和模拟了两种用于微波功率器件的测试电路,并且设计了与之配套的测试夹具.采用矢量网络分析仪对该测试电路和夹具在3～8GHz范围内进行了小信号测试.模拟和测试结果都表明,采用扇形线的测试电路性能较好.最后采用该电路和夹具对C波段AlGaN/GaN HEMT微波功率器件进行了微波功率测试,测试频率为5.4GHz.实验测得最大功率增益为8.75dB,最大输出功率为33.2dBm.     

Optimization of Material and Process for Fine Pitch LVSoP Technology

For the formation of solder bumps with a fine pitch of 130 μm on a printed circuit board substrate, low‐volume solder on pad (LVSoP) technology using a maskless method is developed for SAC305 solder with a high melting temperature of 220°C. The solder bump maker (SBM) paste and its process are quantitatively optimized to obtain a uniform solder bump height, which is almost equal to the height of the solder resist. For an understanding of chemorheological phenomena of SBM paste, differential scanning calorimetry, viscosity measurement, and physical flowing of SBM paste are precisely characterized and observed during LVSoP processing. The average height of the solder bumps and their maximum and minimum values are 14.7 μm, 18.3 μm, and 12.0 μm, respectively. It is expected that maskless LVSoP technology can be effectively used for a fine‐pitch interconnection of a Cu pillar in the semiconductor packaging field.     

A Novel Three-Dimensional Packaging Method for Al-Metalized SiC Power Devices

A novel three-dimensional packaging method for Al-metalized SiC power devices has been developed by means of Au stud bumping technology and a subsequent vacuum reflow soldering process with Au-20Sn solder paste. Al-metalized electrodes of a SiC power chip can be robustly assembled to a direct bonded copper (DBC) substrate with this method. The bump shear strength of a Au stud bump on an Al electrode of a SiC chip increased with bonding temperature. The die shear strength of a SiC chip on the DBC substrate increased with the number of Au stud bumps which were preformed on the Al electrode. The bonded SiC-SBD chips on a DBC substrate were aged at 250 ${^circ}{rm C}$ in a vacuum furnace and the morphologies, die shear strength and electrical properties were investigated after a certain aging time. After 1000 h aging at 250 ${^circ}{rm C}$, the electrical resistance of the bonded SiC-SBD chips only increased about 0.4%, the residual die shear strength was much higher than that of the IEC749 (or JEITA) standard value, and little morphological change was observed by a micro-focus X-ray TV system. Very little diffusion between Au stud bumps and Au-20Sn solder was observed by scanning electron microscope (SEM) equipped with an energy dispersed X-ray analyzer (EDX). Intermetallic compounds (IMC) evolved at the interface of chip/solder and chip/Au stud bumps after 1000 h aging at 250 ${^circ}{rm C}$. With this method, power devices with Al bond pads can be three-dimensionally packaged.      

一种小点间距LED显示屏画面偏色的补偿方法

针对小点间距LED显示屏常见的两种偏色问题,即白平衡偏色和首行偏暗,设计了一种可以同时解决两种问题的电路。由于红绿蓝三种LED的寄生参数不同,使得白平衡偏色。多行扫中第一行扫的列电压较其他列高时,导致第一行的LED导通电流偏低,使得第一行显示效果偏暗。该解决方案对两种情况下的PWM驱动信号进行补偿,并且提供了不同的补偿等级,补偿后,显示画面灰度精准、均匀性高,很好地解决了以上两种问题。     

大型液晶显示用COF带的细节距线路形成

概述了大型液晶显示用COF带的特征和制造技术以及细节距线路形成技术。