Statistical Design of a 10 bit Current Division Network

The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2 m process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.     

Analog VLSI Design Constraints of Programmable Cellular Neural Networks

Analog parallel signal processing systems, like cellular neural networks (CNN's), intrinsically have a high potential for perception-like signal processing tasks. The robust design of analog VLSI requires a good understanding of the capabilities as well as the limitations of analog signal processing. Implementation-oriented theoretical methods are described to compute the effect of all types circuit non-idealities with random or systematic causes on the static and dynamical behavior of CNN's and to derive specifications for the cell circuit building blocks. The fundamental impact of transistor mismatch on the trade-off between the speed, accuracy and power performance of CNN chips is demonstrated. A design methodology taking into account the effect of transistor mismatch is proposed and experimental results of a CNN chip implementation designed with this method are discussed.     

基于统计结构梯度特征的行人检测

针对自然背景下的行人检测问题,从人体最显著的轮廓信息出发,提出一种基于统计结构梯度(SSG,Statistical Structural Gradient)的行人检测算法。采用支持向量机(SVM,Support Vector Machine)算法对数据库中行人样本的SSG特征进行训练,得到行人检测分类器。提出的SSG算法在sobel图像中仅做结构统计和角度幅值计算,能够采用积分图加速行人检测速度。对INRIA数据库中的288张样本进行测试,误检率(FPPW,False Positives Per Window)为10-5,检测率等于90.89%。     

VLSI集成电路参数成品率及优化研究进展

VLSI的参数成品率是与制造成本和电路特性紧密相关的一个重要因素,随着集成电路(IC)进入超深亚微米发展阶段,芯片工作速度不断增加,集成度和复杂度提高,而工艺容差减小的速度跟不上这种变化,因此参数成品率的研究越来越重要.本文系统地讨论了参数成品率的模型和设计技术研究进展,分析不同技术的特点和局限性.最后提出了超深亚微米(VDSM)阶段参数成品率设计和成品率增强面临的主要问题及发展方向.     

典型器件和电路不同剂量率的辐射效应

对几十种不同类型的典型星用器件和电路在不同剂量率辐照下的响应规律及退火特性进行了研究。对双极器件和电路及JFET输入运算放大器电路产生低剂量率损伤增强效应的机理进行了分析。结果显示,器件类型不同,失效模式也相异。其典型的失效模式表现为4种:a)仅有低剂量率辐照损伤增强效应;b)既有低剂量率辐照损伤增强效应,又有时间相关效应;c)仅有时间相关效应;d)无不同剂量率辐照损伤间的差异。     

6端口CMOS寄存器堆设计

高性能超标量处理器完成多条指令并行,需要寄存器堆提供多端口、高速访问.本文介绍一个0.18μmCMOS工艺下的四读二写6端口寄存器堆的全定制设计,它采用改进的多端口存储器单元结构和基于NAND结构的低功耗译码器,并且设计了内部时钟生成部件来提高工作频率.寄存器堆通过功能验证和性能测试,可以工作在450MHz频率上,功耗为36mW,面积0.06mm2,参考综合结果具有高速、低功耗和面积小的特点.     

基于配价结构和语义依存关系的句法分析统计模型

目前主流的词汇化句法分析方法仅仅考虑词语之间的语义依存关系,而没有引入语义搭配和语义类等语义信息．“配价”是词语的一个比较本质的特点,一旦一个词语的配价结构确定下来,它应该和怎样的词进行搭配也就比较清楚了,从而也可以比较直接地导出句子的结构．本文结合中心词驱动句法分析模型,提出了基于配价结构和语义依存关系的句法分析模型．模型在规则的分解及概率计算中引入丰富的语义信息,既包括语义依存信息,也包括配价结构等语义搭配信息．用改进的句法分析模型进行句法分析实验,实验结果表明,精确率和召回率分别为88.76％和87.43％,综合指标F值比Collins的中心词驱动句法分析模型提高了6.65个百分点．     

Fault diagnosis in reconfigurable VLSI and WSI processor arrays

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The divide and conquer technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(V^1/2) for the processor arrays considered in this paper, where V is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.     

环行器波导结构设计探讨

在介绍结式环行器波导结构设计思路和方法的基础上,对其中应注意的几个主要问题进行了分析、归纳和总结。     

一种VLSI设计到赋权超图的转换系统

本文基于VLSI划分问题的需要,提出了一种VLSI设计到赋权超图转换算法.该算法解决的关键问题是,它读取和遍历Verilog语言描述的树状结构VLSI设计,将其转换为赋权超图并存储为指定的文件存储格式,从而有效地将VLSI划分问题转换为超图划分优化问题.进而,本文给出了VLSI设计到赋权超图的转换系统（VLSI/Hypergraph Converter,VHC）的处理流程图,并在Windows平台下用C＋＋设计实现了VHC系统.实验及分析表明,该系统能正确地将Verilog语言描述的门级CPU测试用例转换为赋权超图,避免了直接在VLSI线网上进行划分,提高了VLSI划分的效率.     

结构设计在电子设备中的重要性研究

在分析当代电子设备结构特征及环境对其影响的基础上,讨论了电子设备在结构设计中需要考虑的问题,并从热设计、电磁兼容设计和防腐蚀设计三个方面详细介绍了结构设计的重要性和设计方法。     

低压/低功耗VLSI中器件结构的设计

随着个人数据处理和通信技术的发展,设备的小型化推动着ＶＬＳＩ向低压、低功耗的工作方式转化。但硅ＶＬＳＩＡ电路在室温（Ｔ＝３００Ｋ）下工作,会受到各种因素的限制,如静态漏电流、穿通、速度等。文章从ＭＯＳ器件的物理角度,阐述低压、低功耗ＭＯＳ集成电路中器件结构的设计,并给出了器件的模拟特性。     

Robust Design of Basic Low Voltage CMOS Transconductors

Two new low voltage transconductors are introduced and the statistical design of these transconductors are presented. The circuits operate in the saturation region with fully balanced input signals. Initial circuit simulation results are given. Response surface methodology and design of experiment techniques are used as statistical VLSI design tools together with the statistical MOS (SMOS) model. The response surfaces obtained for the two transconductors show the trade-off between area and functional yield. Using these contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours also provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.     

军用电子设备结构设计方案有关问题探讨

军用电子设备的结构设计方案作为项目总体方案的重要组成部分,是设备研制过程中结构工程设计的依据.文中阐述了拟制结构设计方案的重要性,详细讨论了结构设计方案拟制的依据、内容和实施问题.     

一种新型低噪声电流控制逻辑的分析与设计

本文绘出了一种新型电流控制逻辑的电路结构和工作原理，并由此提出了该逻辑的优化设计方法。通过采用恒定工作电流和限制电路的输出逻辑摆幅，电流控制逻辑能避免静态CMOS电路工作时引入的瞬态开关噪声电流。理论分析和电路模拟结果都表明，和静态CMOS电路相比，电流控制逻辑的峰值开关电流下降了近两个数量级．该逻辑可应用在高性能的模／数混合集成电路中。     

Challenges and opportunities toward fully automated analog layout design

Realizing the layouts of analog/mixed-signal (AMS) integrated circuits (ICs) is a complicated task due to the high design flexibility and sensitive circuit performance. Compared with the advancements of digital IC layout automation, analog IC layout design is still heavily manual, which leads to a more time-consuming and error-prone process. In recent years, significant progress has been made in automated analog layout design with emerging of several open-source frameworks. This paper firstly reviews the existing state-of-the art AMS layout synthesis frameworks with focus on the different approaches and their individual challenges. We then present recent research trends and opportunities in the field. Finally, we summaries the paper with open questions and future directions for fully-automating the analog IC layout.     

Present and Future Industrial Applications of Bio-Inspired VLSI Systems

Biology can be a rich source of inspiration for engineers. In particular, designers of VLSI processing circuits and systems can draw inspiration from several aspects of the brain. Inspired from evolution, the opportunistic exploitation of all the properties of the technology provides very efficient analog circuit techniques. The collective computation carried out by the brain in its massively parallel architecture can be emulated on silicon. Strategies like learning and adaptation are very beneficial to VLSI processing. The same is true for the unusual ways used by the brain to represent signals and information. Four industrial chips developed with this bio-inspired approach are described, as well as several experimental circuits that demonstrate its potential for future products.     

低阈值量子结构激光器的优化结构设计

针对低阈值半导体量子结构激光器（简称量子结构激光器）,包括量子阱、量子线和量子点结构,给出了一个完整简便的方法用以优化设计最低阈值条件所需要的有源区结构。以对数形式给出了量子结构激光器材料增益和注入载流子浓度的关系,并且以ＩｎＧａＡｓ（Ｐ）／ＩｎＰ量子阱激光器和ＩｎＡｓ／ＧａＡｓ自组装量子点结构激光器为例,分别计算了为得到最低阈值电流所需要的量子阱阱数和自组装量子点的面密度以及激光器的腔长。     

Design of multi-mode application-specific cores based on high-level synthesis

In a mobile society, more and more devices need to continuously adapt to changing environments. Such mode switches can be smoothly done in software using a general purpose processor or a digital signal processor. However hardware cores only can cope with both throughput and power consumption constraints. Reconfigurable hardware platforms provided by FPGA devices offer partial reconfiguration at runtime. However they require too long reconfiguration times and they cannot satisfy mobile device power consumption requirements. In this article we propose a methodology to map selected groups of DSP tasks to multi-mode cores using conventional hardware technologies.